Conexant RC144D, Руководство дизайнера

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RC56D, RC336D, and RC144D Modem Device Sets Designer’s Guide
1154
Conexant
4-1
4. PARALLEL HOST INTERFACE
The modem supports a 16550A interface in parallel interface versions. The 16550A interface can operate in FIFO mode or
non-FIFO mode. Non-FIFO mode is the same as 16450 interface operation. FIFO mode unique operations are identified.
4.1 OVERVIEW
The parallel interface registers and the corresponding bit assignments are shown in Table 4-1.
The modem emulates the 16450/16550A interface and includes both a 16-byte receiver data first-in first-out buffer (RX FIFO)
and a 16-byte transmit data first-in first-out buffer (TX FIFO). When FIFO mode is selected in the FIFO Control Register
(FCR0 = 1), both FIFOs are operative. Furthermore, when FIFO mode is selected, DMA operation of the FIFO can also be
selected (FCR3 = 1). When FIFO mode is not selected, operation is restricted to 16450 interface operation.
The received data is read by the host from the Receiver Buffer (RX Buffer). The RX Buffer corresponds to the Receiver Buffer
Register in a 16550A device. In FIFO mode, the RX FIFO operates transparently behind the RX Buffer. Interface operation is
described with reference to the RX Buffer in both FIFO and non-FIFO modes.
The transmit data is loaded by the host into the Transmit Buffer (TX Buffer). The TX Buffer corresponds to the Transmit
Holding Register in a 16550A device. In FIFO mode, the TX FIFO operates transparently behind the TX Buffer. Interface
operation is described with reference to the TX Buffer in both FIFO and non-FIFO modes.