Conexant RC144D, Руководство дизайнера

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RC56D, RC336D, and RC144D Modem Device Sets Designer’s Guide
1154
Conexant
3-25
3.2.2 Parallel Host Bus Timing
The parallel host bus timing is listed in Table 3-14 and illustrated in Figure 3-8.
Table 3-14. Timing - Parallel Host Bus
Symbol Parameter Min Max Units
READ (See Notes 1, 2, 3, 4, 5, and 6)
t
AS
Address Setup 5 – ns
t
AH
Address Hold 10 – ns
t
CS
Chip Select Setup 0 – ns
t
CH
Chip Select Hold 10 – ns
t
RD
~HRD Strobe Width 51 – ns
t
DD
Read Data Delay – 45 ns
t
DRH
Read Data Hold 10 – ns
WRITE (See Notes 1, 2, 3, 4, 5, and 6)
t
AS
Address Setup 5 – ns
t
AH
Address Hold 10 – ns
t
CS
Chip Select Setup 0 – ns
t
CH
Chip Select Hold 10 – ns
t
WT
~HWT Strobe Width 50 – ns
t
DS
Write Data Setup (see Note 4) – 35 ns
t
DWH
Write Data Hold (see Note 5) 5 – ns
Notes:
1. When the host executes consecutive Rx FIFO reads, a minimum delay of 2 times the internal CPU clock cycle plus
15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of ~HRD to the falling edge of the next Host Rx
FIFO ~HRD clock.
2. When the Host executes consecutive Tx FIFO writes, a minimum delay of 2 times the internal CPU clock cycle plus
15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of ~HWT to the falling edge of the next Host Tx
FIFO ~HWT clock.
3. t
RD
, t
WT
= t
CYC
+ 15 ns.
4. t
DS
is measured from the point at which both ~HCS and ~HWT are active.
5. t
DWH
is measured from the point at which either ~HCS and ~HWT become inactive.
6. Clock frequency = 28.224 MHz clock.