Conexant RC144D, Руководство дизайнера

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RC56D, RC336D, and RC144D Modem Device Sets Designer’s Guide
1154
Conexant
3-23
3.2 INTERFACE TIMING AND WAVEFORMS
3.2.1 External Memory Bus Timing
The external memory bus timing is listed in Table 3-13 and illustrated in Figure 3-7.
Table 3-13. Timing - External Memory Bus
Symbol Parameter Min Typ. Max Units
t
FI
Internal Operating Frequency 28.224 MHz
t
CYC
Internal Operating Clock Cycle 35.43 ns
Read
t
AS
~READ High to Address Valid – 11.2 12.5 ns
t
ES
~READ High to ES Valid – 12.2 13.5 ns
t
RW
~READ Pulse Width 17.72 124.01 ns
t
RDS
Read Data Valid to ~READ High 6.3 5.7 – ns
t
RDH
~READ High to Read Data Hold 0 – ns
Write
t
AS
~WRITE High to Address Valid – 11.2 12.5 ns
t
ES
~WRITE High to ES Valid – 12.2 13.5 ns
t
WW
~WRITE to ~WRITE Pulse Width 17.72 124.01 ns
t
WTD
~WRITE Low to Write Data Valid – 7.1 8.0 ns
t
WTH
~WRITE High to Write Data Hold 5.0 – ns
Notes:
1.
ES = ~RAMSEL or ~ROMSEL.
2. Read pulse width and write pulse width:
RAM: t
RW
, t
WW
= 0.5 t
CYC
= 17.72 for Non-Extended Cycle Timing
ROM: t
RW
, t
WW
= 3.5 t
CYC
= 124.01 for Extended Cycle Timing
3. Memory speed determination:
RAM: tACCESS = tCYC - tES - tRDS = 35.43 - 13.5 - 6.3 = 15.63 ns (i.e., use 15 ns memory)
ROM: tACCESS = 4(tCYC) - tES - tRDS = 4(35.43) - 13.5 - 6.3 = 121.92 ns (i.e., use 90 ns memory).
4. Output Enable to Output Delay Timing:
RAM: t
OE
= t
RW
- t
RDS
= 0.5(t
CYC
) - t
RDS
= 17.72 - 6.3 = 11.42 ns
ROM: t
OE
= t
RW
- t
RDS
= 3.5(t
CYC
) - t
RDS
= 124.01 - 6.3 = 117.71 ns.