CommTech FASTCOM SuperFASTCOM, Справочник по аппаратуре

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due to one of the clocks temporarily gapped, ’CEC’ status bit must be checked for ’0’
before writing a command bit.
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Carrier Auto-detect in HDLC Mode
The carrier detect (CD) input pin is supposed to enable and disable reception in clock
modes 0, 2, 3, 6 and 7. In HDLC/PPP mode this function is not working properly and
thus should not be enabled with bit CCR1:CAS.
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Receiver in Extended Transparent Mode Does Not Initialize
When attempting to use Extended Transparent Mode (raw bits), it appears as though
the receiver does not activate. It unclear whether this is a bug in the PEB20534 or
whether it was done by design, but the port that will be receiving in Ext. Trans. Mode
must be initialized in clock mode 1 with a clock present on the RT pins. It can then be
switched to any other clock mode and will operate correctly.
Workaround: If your configuration already uses an external receive clock, simply
initialize the card in clock mode 1 (CCR0:CM2..CM0 = ‘001’) with a clock present on the
RT pins and then change to whatever clock mode you wish to use. If you do not have
an external clock, you can utilize the PROGCLK output pins that are located on the
DB25 connector for port 1 at pins 20 and 23. Jumper the PROGCLK pins to the RT
pins of your receiving port and initialize the card in clock mode 1.