CommTech FASTCOM SuperFASTCOM, Справочник по аппаратуре

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ERRATA
The errata listed below are known issues with the either Superfastcom board or the PEB20534
controller itself. For more information regarding any of these issues, please contact
Commtech
technical support .
•
Serial Bus Configuration Timing Modes
The SuperFastcom was not designed to make use of Serial Bus Configuration timing
modes 1 and 2. Do not attempt to configure CCR0:SC(2..0) to use these modes as
they will not work correctly.
•
Maximum Value of Baudrate Generator
The maximum value ’BRM’ in register BRR must not exceed M = 14 (the specified
maximum value is M = 15). This limits the baud rate generator unit to frequency division
factors in the range k = 1... 1,048,576, instead of k = 1... 2,097,152.
•
DPLL Algorithm for FM0, FM1 and Manchester Encoding
Recovering the clock from an FM0-, FM1- or Manchester-encoded receive data stream
using the DPLL circuitry is not working. The DPLL-asynchronous interrupt (PLLA)
occurs continuously.
•
HDLC Mode: False Receive Status Byte
The receive status byte RSTA belonging to an already received frame is overwritten by
0x00 if the following two conditions are met:
1. The interframe timefill number of ’1’ bits between the closing flag and the opening
flag of the next frame is in the range of [1 - 5].
2. The receive CRC checking mode is selected to transfer the receive CRC into the
receive FIFO (CCR2:RCRC = ’1’).
In all cases meeting the first condition, the number of ‘1’ bits is treated as an invalid
HDLC frame. This frame is prevented from being reported or forwarded to the receive
FIFO because of its invalid length. However the serial receive logic calculates a receive
status byte RSTA = 0x00 (invalid frame).
If the receive CRC is selected to be transferred to the receive FIFO (second condition),
the receive status value of the previous valid frame is not yet transferred when
calculating the invalid receive status byte. Thus the original receive status value is
overwritten by 0x00 marking the previous frame as ’invalid’.
Workaround : The error cannot occur if bit CCR2:RCRC is set to ’0’, i.e. receive CRC is
not transferred to the receive FIFO. Otherwise (if CCR2:RCRC = ’1’) reception of less
than 6 consecutive ’1’ bits as interframe timefill must be avoided. This can be achieved
by the transmitter either selecting interframe timefill flag sequences or preamble
transmission.
•
HDLC Mode: Transmission with Shared Flags
If the shared flag option is enabled in HDLC mode via bit CCR1:SFLAG, the first byte of
a frame might be replaced by a ’7E’ flag or ’FF’ octet on the transmit line, depending on
the interframe time fill selection (bit CCR2:ITF). This leads to a damaged transmit
frame.