CommTech FASTCOM SuperFASTCOM, Справочник по аппаратуре

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7
- Data overflow and under run detection
- Timer
Protocol Support
Address Recognition Modes
- Mode 0 - No address recognition
- Mode 1 - 8-bit (high byte) address recognition
- Non-Auto Mode - 8-bit (low byte) or 16-bit (high and low byte) address recognition
General
On-chip Rx and Tx data buffer (the buffer size is 128 32-bit words each)
Programmable buffer size in transmit direction per channel; buffer allocation in receive
direction on request.
Programmable watermark for receive channels to control transfer of receive data to
host memory.
Two programmable watermarks for each transmit channel, i.e. one controlling data
loading from host memory and one controlling transfer of transmit data to the
corresponding Serial Communication Controller (SCC).
Internal test loop capability.