CommTech FASTCOM SuperFASTCOM, Справочник по аппаратуре

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Workaround : It is recommended to disable shared flag transmission by setting bit
CCR1:SFLAG = ’0’.
Note: Reception of frames with shared flags is always possible and neither
affected by this erratum nor by setting of bit CCR1:SFLAG. Thus networking with
other HDLC equipment supporting shared flags is not restricted.
•
Asynchronous PPP Mode: Reception
In asynchronous PPP mode the SCC receiver expects a back-to-back stream of
ASYNC characters. Once synchronized on the first ASYNC character the receiver
expects further octets back-to-back in a fixed scheme determined by the (8, N, 1)
character format. The receiver does not synchronize again on subsequent ASYNC
characters.
Workaround : Do not attempt to configure ASYNC PPP mode, to realize asynchronous
PPP mode it is recommended to configure the SCC in ASYNC mode, implementing
CRC calculation and character mapping in software. Examples for fast CRC calculation
and the character mapping specification are given in RFC 1662 (July 1994) document.
•
Extended Transparent Mode: Minimum Frame Length
If the frame length in extended transparent mode is programmed to one, an XDU
interrupt is generated with all its consequences (transmit SCC stops).
Workaround : Frame lengths of 2 or more bytes should be used instead. If a 1-byte
frame shall be sent, an idle character should be attached to it.
•
HDLC Automode: Full-duplex Operation
In HDLC Automode the transmission of an I-frame might be spoiled by simultaneous
reception of a frame, sometimes resulting in endless repetition of a byte or in failure of
the responding S-frame. Then this channel does not respond autonomously to further
reception events.
Workaround : None. Do not use full-duplex Automode.
•
Command Execution (CEC) Status Bit Error With External Clocking
In general the PEB20534 supports external clock gapping in any clock mode in which
the internal transmit or receive clock is supplied via the dedicated RxClk and/or TxClk
pins. If one of the clocks is externally gapped, the respective receive or transmit block
remains in its current static condition until the clock signal is active again. Any
command bit in register CMDR (e.g. ’XRES’ and ’RRES’) effects either the transmit or
receive logic and command execution only depends on this block and its clock supply
respectively. Nevertheless all commands are forwarded to both transmit and receive
block and command execution must be reported internally by both blocks to reset status
bit STAR:CEC. Another command is only accepted if ’CEC’ bit is cleared.
Example : The SCC is configured in clock mode 0a, a clock signal is provided at pin
TxClk but pin RxClk is supplied with a constant value (no clock signal or gapped). A
transmitter reset command applied by write access to register CMDR will be executed
by the transmit block, but status bit ’CEC’ remains active afterwards, because the
receive block cannot report command execution without clock supply. Any further
command will be ignored while ’CEC’ bit is active.
Workaround : Transmit and receive blocks must be supplied with clock signals in
general. Because reset of the command execution (CEC) status bit might be delayed