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AN211
Rev 0.5 | 21/24
www.cmostek.com
7
6
5
4
3
2
1
0
WRF
-
ENW
CLRW
WIDL
PS2
PS1
PS0
Disable : (No action)
WDSFWP
Enable : To Write the WDTCR will be deny
Disable : To Write the WDTCR will be accept
HWBS2
Enable : In addition to power-up, the reset from RST-pin will also force MCU to boot from ISP-memory, if ISP-memory is
configured
Disable : Where MCU boots from is determined by
HWBS
ENLVRO
Enable : Enable Low-Voltage Reset (LVR) when Vdd less then 3.7V
Disable : Disable LVR
ENLVRC
Enable : Enable Low-Voltage Reset (LVR) when Vdd less then 2.5V
Disable : Disable LVR
BODRE
Enable : Enable Low-Voltage Reset (LVR)
Disable : Disable LVR
BODWP
Enable : Enable LVFWP (Low-Voltage Flash-Write Protection) while IAP or ISP programming
Disable : Disable LVFWP
P40IOE
Enable : Enable the P4.0 is in “Input Only mode” after Power On Reset
Disable : The P4.0 is in default “Quasi-Bidirectional mode”
P41IOE
Enable : Enable
the P4.1 is in “Input Only mode” after Power On Reset
Disable : The P4.1 is in default “Quasi-Bidirectional mode”
{BO1S1O,BO1S0O}
{0, 0} : BOD1 detects the level at 2.0V on VDD
{0, 1} : BOD1 detects the level at 2.4V on VDD
{1, 0} : BOD1 detects the level at 3.7V on VDD
{1, 0} : BOD1 detects the level at 4.2V on VDD
BO0REO
Enable : BOD0 will trigger a RESET event to CPU on AP program start address
Disable : BOD0 can not trigger a RESET to CPU
BO1REO
Enable : BOD1 will trigger a RESET event to CPU on AP program start address
Disable : BOD1 can not trigger a RESET to CPU
NSWDT
1
HWWIDL
HWPS[2:0]
set
load
load