Cisco HyperSwitch A100, Руководство пользователя

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Specifications
and Product Compliance
Specifications
and
Product
Compliance
Table 1-2
lists
the
HyperSwitch
A100
ATM
switch
specifications
Component
Switch
architecture
Switch
capacity
Buffer
Cell delay
Control processor
Path
Setting
Specification
Input
and
output
buffer
type
2.4 Gbps 155 Mbps
16
Input
buffer
2048
cells
per
two lines
Output
buffer
128
cells
per
two
lines
20 microseconds
to milliseconds
Internal 32-bit
Reduced
Instruction
Set Computing
RISC
processor
4096 channels
per
line
VP/VC
routing
supported
All
12
bits
of
VPI
Lower 12-x
bits
of 16
bits
of
VCI
PVC
fixed path
automatically
set
per
PVC
information
Multicast
connectable
Can
be
added/changed
from
external terminal
SVC
switched
path
SNMP
EIA/TIA-232
Peak
rate
can
be
set
per
channel
Specification
Height
165
mm
approximately
1/2
in
Width
435
mm
approximately
17 1/8
in
Depth
420
mm
approximately 16 5/8
in
General
15 kg approximately
33
lb
Fully
equipped
17
kg approximately
37
1/2 lb
Table 1-2
Device
Switch
HyperSwitch
A100
ATM
Switch
Specifications
Control
system
Number
of concurrent connectable
channels
NMS
Interface
MAT
interface
Traffic
Policing
control
Control
Congestion control
Back
pressure
output
line switch
input
line
Priority
control Cell
loss
Two levels
Cell
delay
Two
levels
Line
Maximum
line
speed
155
Mbps
per
line
Maximum
number
of
lines
per
16 lines
switch
Line
interface
types
SONET OC3/SDH STM1
155
Mbps
4B/5B
TAXI FDDI 100 Mbps
Table 1-3
lists
the
HyperSwitch
A100
physical specifications
Table 1-3
HyperSwitch
AlDO
Physical
Specifications
Item
Dimensions
Weight
1-2
Cisco HyperSwitch
A100
User Guide