MUX/DMUX
Figure
B-2
MUX/DMUX
Card
Block
Diagram
G/B1
MI0
PA20
Guaranteed
G/B1
Mlo
pA215
G/B1Ml0
iiThjM
G/B1
Ml0
PA20
j1jj_
Best
effort
G/B0
MI0
PA215
G/B0
Ml1
iiim
BPB
0-15
BPGM
________
_____
________
BPB
0-15
SRAM
BPBM
ATOM
SW
LINF2I
IIx-
_____
____
DMUX
LINF
2i1
_______________________________
MUX
LSI
Note
The
static
random-access
memory
SRAM
comprises
an input
buffer
shared
by two
lines
Five
SRAMs
each
of
32Kx9
bits save
2K
cell
and
switch-specific
overhead
data
Table
B-i
Conditions
in
Which
FIFO Queues
are
Served
Priority
Level
IBGi
IBGM
IBBi
IBBM
Served
when
back
pressure
BP
is
not
received
and
threshold
is
exceeded
Normal
level
Served
when
BP
is
not
received
and
threshold
is
exceeded
Normal
level
When
BP
is
received
When
BP
is
received
Cell
output
inhibited
Functions
of
the
Expandable
ATM
Output
Buffer
Modular
Switch
B-3
Содержание HyperSwitch A100
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