Cisco 10008, Руководство по установке и настройке, Страница: 22 / 70

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Cisco 10008 Router PRE4 Installation and Configuration Guide
OL-13840-01
Configuring Network Timing
The following steps enable you to configure a clock source:
Step 1
Select a priority for the clock source. The priority is used to select a primary source and one or more
secondary sources, in case of clock failure. Set the clock priority between 1 and 6. The highest priority
is 1.
Router(config)#
network-clock select
<1-6>
Step 2 Select the controller, interface and slot options to source the clock, as shown in Example 1 .
Example 1 Options to Source the Clock
In this example, ‘T’3 is the controller, ‘1:0’ is the serial interface and ‘pre-a’ denotes the active PRE4.
Router(config)# network-clock select 1 T3 5/0/0
Router(config)# network-clock select 1 interface serial 5/0/0/1:0
Router(config)# network-clock select 1 slot pre a
Note ‘pre-b’ denotes the standby PRE4.
Step 3 After selecting the PRE4, select the parameters for the T1/E1 BITS input configuration.
T1 BITS Input
Router(config)# network-clock select 1 slot pre-a t1 {esf | sf} {b8zs | ami}
E1 BITS Input
Router(config)# network-clock select 1 slot pre-a e1 {crc4 | no-crc4} {hdb3 | ami}
For examples of T1 and E1 BITS input configuration, see Example 5 and Example 6 respectively.
Selecting Participating Subslots
Use the network-clock participate command in global configuration mode to configure individual
subslot(s) that source the Network Timing clock. The range for slots is 1 to 8 and for subslots the range
is 0 to 1.
Router(config)# network-clock participate
[ slot / subslot ]
Reverting to a Higher Priority Clock
The network-clock revertive command allows you to automatically switch the clock to a higher priority
after it recovers from a previous failure.
Router#
network-clock revertive ?
<cr>
Verifying the Network Timing Configuration
The show network-clock command displays the clock sources configured, with their status and priority,
and can be extended to display information about the daughter board and other digital phased locked
loop (DPLL) information, as shown in
Table 7 .