Cirrus Logic CS4399, Руководство пользователя

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16 DS1113F1
CS4399
3 Characteristics and Specifications
Table 3-8. Digital Interface Specifications and Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground;
parameters can vary with VL and VP; typical performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; min/max performance
data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; T
A
= +25°C; C
L
= 60 pF.
Parameters 1
1.See Table 1-1 for serial and control-port power rails.
Symbol Minimum Maximum Units
Input leakage current 2,3
2.Specification is per pin.
3.Includes current through internal pull-up or pull-down resistors on pin.
LRCK1, DSDB/LRCK2
SDIN1, SCLK1, DSDA/SDIN2, DSDCLK/SCLK2
HP_DETECT
SDA, SCL
INT, RESET
I
in
—
—
—
—
— ±4
±3
±100
±100
±100
µA
µA
nA
nA
nA
Internal weak pull-down — 550 2450 k

Input capacitance — — 10 pF
INT current sink (V
OL
= 0.3 V maximum)
— 825 — µA
VL Logic (non-I 2 C) High-level output voltage (I
OH
= –100 µA)
Low-level output voltage
High-level input voltage
Low-level input voltage
V
OH
V
OL
V
IH
V
IL
0.9•VL
—
0.7•VL
—
—
0.1•VL
—
0.3•VL
V
V
V
V
VL Logic (I 2 C only) Hysteresis voltage (Fast Mode and Fast Mode Plus)
Low-level output voltage
High-level input voltage
Low-level input voltage
V
HYS
V
OL
V
IH
V
IL
0.05•VL
—
0.7•VL
—
—
0.2•VL
—
0.3•VL
V
V
V
V
HP_DETECT 4
4.The HP_DETECT input circuit allows the HP_DETECT signal to be as low of a voltage as VCP_FILT– and as high as VP. Section 4.4.1 provides
configuration details.
High-level input voltage
Low-level input voltage
V
IH
V
IL
0.93•VP
—
—
2.0
V
V
HP_DETECT current to VCP_FILT– 4 I
HP_DETECT
1.00 2.91 µA
Table 3-9. CLKOUT Characteristics
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; C
L
= 60 pF; PLL reference input must meet the phase-noise mask specified in Fig. 4-12 ; T
A
= +25°C; Output jitter is measured from 100 Hz
to half of the output frequency.
Parameters Symbol Minimum Typical Maximum Units
CLKOUT output frequency f
CLKOUT
2.8224
5.6448
7.5264
11.2896
3
6
8
12
3.072
6.144
8.192
12.288
MHz
MHz
MHz
MHz
CLKOUT output duty cycle — 40 50 60 %
CLKOUT output TIE jitter (RMS) CLKOUT_SRC_SEL = 01 t
JIT
— 500 — ps
Table 3-10. PLL Characteristics
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; PLL reference input must meet the phase-noise mask specified in
Fig. 4-12 ; T
A
= +25°C.
Parameters Symbol Minimum Typical Maximum Units
PLL output frequency f
out
22.5792 24 24.576 MHz
PLL lock time t
Lock
— 620 1000 µs
PLL reference clock input — —
—
—
—
—
—
—
—
—
— 11.2896
22.5792
12.2880
24.5760
9.6000
19.2000
12.0000
24.0000
13.0000
26.000
—
—
—
—
—
—
—
—
—
— MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL reference clock input jitter — — — 50 ps