Cirrus Logic CS4399, Руководство пользователя

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DS1113F1 13
CS4399
3 Characteristics and Specifications
Other characteristics
for AOUTx
Interchannel gain mismatch (defined in Table 3-1 ) — ±0.1 — dB
Interchannel phase mismatch (defined in Table 3-1 ) — ±0.05 — °
Output offset voltage: Mute (defined in Table 3-1 ) — ±0.5 ±1 mV
Gain drift (defined in Table 3-1 ) — ±100 — ppm/°C
Load resistance (R
L
) 600 — —

Load capacitance (C
L
) — — 1 nF
Turn-on time (defined in Table 3-1 ) — — 10 ms
Click/pop during PDN_HP enable or disable A-weighted — — –60 dBV
1.This table also applies to external VCP_FILT supply mode: CS4399 power up procedure is per description in Section 5.10.1 ; EXT_VCPFILT = 1; VCP_
FILT+ and VCP_FILT– comply to Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN setting becomes don’t care.
2.One LSB of triangular PDF dither is added to PCM data.
3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table.
4.DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index.
5.The volume must be configured as indicated to achieve specified output characteristics.
6.Output test configuration. Symbolized component values are specified in the test conditions.
Table 3-5. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics
Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired
sample rate by multiplying the given characteristic by Fs. Single-Speed Mode refers to 32-, 44.1-, and 48-kHz sample rates. Double-Speed Mode refers
to 88.2- and 96-kHz sample rates. Quad-Speed Mode refers to 176.4- and 192-kHz sample rates. Octuple-Speed Mode refers to 352.8- and 384-kHz
sample rates. MCLK_INT is an integer multiple of Fs; HPF disabled; no DC offset applied; group delay does not include serial port delay.
Parameter Minimum Typical Maximum Units
Fast Roll-Off
( FILTER_SLOW_FASTB = 0)
Single-Speed Mode 1
Passband
2
to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
8.44 3
—
—
— 0.4535
4
0.49
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner 5 –0.01 — +0.01 dB
Stopband 0.547 — — Fs
Stopband attenuation
6
PHCOMP_LOWLATB = 0
PHCOMB_LOWLATB = 1
110
7
105
—
— —
— dB
dB
Group delay (linear phase) PHCOMB_LOWLATB = 1 — 39.5/Fs 8 — s
Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 6.3/Fs
9
— s
Deemphasis error
10
(Relative to 1 kHz)
Fs = 44.1 kHz — — ±0.14 dB
Fast Roll-Off
( FILTER_SLOW_FASTB = 0)
Double-Speed Mode
1
Passband 2 to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
7.77
—
—
— 0.227
0.48
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB
Stopband 0.583 — — Fs
Stopband attenuation
6
80 — — dB
Group delay (linear phase) PHCOMB_LOWLATB = 1 — 22.3/Fs — s
Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 7.5/Fs — s
Table 3-4. Analog Output Characteristics (HV_EN = 1)
1
(Cont.)
Test conditions (unless otherwise specified): Fig. 2-1 shows CS4399 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless specified
otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with VA =
VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; T
A
= +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK = 44.1-kHz mode);
PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency f
XTAL
= 22.5792 MHz); Volume = 0 dB; when testing in DSD processor
mode, DSD_ZERODB = 1 ; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external impedance on REFx.
PCM and DSD Processor Mode Parameter 2,3,4 Minimum Typical Maximum Units
Test Load
AOUTA
C
LA
REFA
R
LA
Measurement
Device
–
+
–
+ AOUTB
REFB
CH1
CH2
C
LB
R
LB