Cirrus Logic CS4399, Руководство пользователя

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6 DS1113F1
CS4399
1.3 Pin Descriptions
1.3 Pin Descriptions
Table 1-1. Pin Descriptions
Pin Name
QFN
Pin #
WLCSP
Ball
Power
Supply
I/O Pin Description
Internal
Connection
Digital I/O
Driver
Digital I/O
Receiver
ADR 30 C2 VL I Address Bit (I²C). In I²C Mode, ADR is a chip address pin. — — —
CLKOUT 33 B2 VL O CLK Output. Single-ended clock output sourced from PLL or
buffered crystal.
Weak
pull-down
CMOS
output
—
SCLK1 34 A2 VL I/O Serial Audio Input Bit Clock 1. Serial bit clock for audio data on
the SDIN pins.
Weak
pull-down
CMOS
output
Hysteresis
on CMOS
input
LRCK1 38 B3 VL I/O Serial Audio Input Left/Right Clock. Word-rate clock for the
audio data on the SDIN pins.
Weak
pull-down
CMOS
output
Hysteresis
on CMOS
input
SDIN1 2 A6 VL I Serial Audio Input Data Port. Audio data serial input pin 1. Weak
pull-down
— Hysteresis
on CMOS
input
DSDA/
SDIN2
40 A5 VL I DSD Data Input A/Serial Data In 2. DSD audio or PCM audio
data serial input pin 2.
Weak
pull-down
— Hysteresis
on CMOS
input
DSDB/
LRCK2
29 C1 VL I/O DSD Data Input B/Serial Audio Input Left/Right Clock 2. DSD
audio data serial input pin or word rate clock for the audio data on
the SDIN2 pin.
Weak
pull-down
CMOS
output
Hysteresis
on CMOS
input
DSDCLK/
SCLK2
32 B1 VL I/O DSD Clock Input/Serial Audio Input Bit Clock 2. DSD clock
input. Serial bit clock for audio data on the SDIN2 pin.
Weak
pull-down
CMOS
output
Hysteresis
on CMOS
input
INT
27 C5 VP O Interrupt. When pulled up, works as system interrupt pin. Open
drain, active low programmable.
— CMOS
open-drain
output
—
RESET
28 C4 VP I System Reset. The device enters system reset when enabled. — — Hysteresis
on CMOS
input
SDA 39 B4 VL I/O Serial Control Data I/O (I²C). In I²C Mode, SDA is the control I/O
data line.
— CMOS
open-drain
output
Hysteresis
on CMOS
input
SCL 1 B5 VL I Software Clock (I²C). Serial control interface clock used to clock
control data bits into and out of the CS4399.
— — Hysteresis
on CMOS
input
XTI/MCLK 37 A4 VL I Crystal/Oscillator Input/MCLK In. Crystal or digital clock input
for the master clock.
Weak
pull-down
— Hysteresis
on CMOS
input
XTO 36 A3 VL O Crystal/Oscillator Output. Crystal output. Weak
pull-down
CMOS
output
—
FILT+
FILT– 5
6 D4
D5 VA O Positive/Negative Voltage Reference. Positive/negative
reference voltage for DAC.
— — —
HP_
DETECT
22 F4 VP I Headphone Detect. Can be configured to be debounced on
unplugged and plugged events before it is presented as a
noninterrupt status bit (HPDETECT).
— Hi-Z —
AOUTB
AOUTA
16
14 G3
G4 VCP_
FILT±
O Audio Output. Refer to analog specification table for full-scale
output level.
— — —
REFB
REFA 17
13 E3
E4 VCP_
FILT±
I Output Reference. Reference for analog output. — — —
VL 31 A1 N/A I Logic Power. Input/Output power supply, typ1.8 V. — — —
VD 4 C6 N/A I Internal Digital Power. Internal digital power supply, typically
+1.8 V.
— — —
VA 7 D6 N/A I Analog Power. Power supply for the internal analog section. — — —
VCP 25 D2 N/A I Charge Pump Supply . Provides charge pump voltage to the
analog output circuit.
— — —
VP 26 D1 N/A I Battery supply . Provides voltage to the Class H circuit. — — —
Digital I/O
Analog I/O
Power Supplies