Chassis Plans JXT6966, Техническое описание оборудования

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JXT6966 / JXTS6966 Technical Reference PCI Express Backplane Usage
4-1 CHASSIS PLANS
Chapter 4 PCI Express Backplane Usage
Introduction
PCI Express
®
is a scalable, full-duplex serial interface which consists of multiple communication lanes
grouped into links. PCI Express scalability is achieved by grouping these links into multiple
configurations. A x1 (“by 1”) PCI Express link is made up of one full-duplex link that consists of two
dedicated lanes for receiving data and two dedicated lanes for transmitting data. A x4 configuration is
made up of four PCI Express links. The most commonly used PCIe link sizes are x1, x4, x8 and x16.
PCI Express devices with different PCI Express link configurations establish communication with each
other using a process called auto-negotiation or link training. For example, a PCI Express device or option
card that has a x16 PCI Express interface and is placed into a x16 mechanical/x8 electrical slot on a
backplane establishes communication with a PICMG
®
1.3 SHB using auto-negotiation. The option card’s
PCI Express interface will “train down” to establish communication with the SHB via the x8 PCI Express
link between the SHB and the backplane option card slot.
SHB Edge Connectors
The PICMG 1.3 specification enables SHB vendors to provide multiple PCI Express configuration options
for edge connectors A and B of a particular SHB. These edge connectors carry the PCI Express links and
reference clocks down to the SHB slot on the PICMG 1.3 backplane. The potential PCI Express link
configurations of an SHB fall into three main classifications: server-class, graphics-class and conbo-class.
The specific class and PCI Express link configuration of an SHB is determined by the chipset components
used on the SHB.
In a server-class configuration, the main goal of the SHB is to route as many high-bandwidth PCI Express
links as possible down to the backplane. Typically, these links are a combination of x4 and x8 PCI Express
links.
A graphics-class configuration should provide a x16 PCI Express link down to the backplane in order to
support high-end PCI Express graphics and video cards. Graphics-class SHB configurations also provide as
many lower bandwidth (x1 or x4) links as possible.
A combo-class configuration is provided by SHBs like the JXT6966 or JXTS6966. These system host
board types have PCI Express hardware and software implementations that are capable of combining links
to support either server or graphics-class PICMG 1.3 backplane configurations.
The PCI Express links on the JXT6966 / JXTS6966 connect directly to the processors. These links can
operate as either PCI Express 2.0 or PCI Express 1.1 links based on the end-point devices on the backplane
that connect to the SHB. In addition to automatically configuring themselves for either PCIe 2.0 or PCIe
1.1 operations, the links also configure themselves for either graphics or server-class operations. In other
words, the multiple x4 links from the processors; links A0, A1, A2 and A3, can be combined into a single
x16 PCIe electrical link or multiple x8 links on a backplane. The CPU’s x4 links can train down to x1
links, but cannot bifurcate into multiple x1 links. The PCIe link (B0) from the board’s PCH has a x4
default configuration and can be made to bifurcate into four, x1 PCIe links with a factory modification to
the JXT board. Contact Chassis Plans if you require this B0 link configuration change. An optional
PEX10 module connected to a dual-processor JXT6966 provides more backplane links than are currently
supported in the PICMG 1.3 specification. This JXT6966 capability provides additional PCI Express
bandwidth and option card support in the system design.
In addition to the standard PICMG 1.3 edge connector PCIe interfaces and the PEX10 expansion links, the
JXT boards also have an additional x1 link available for use on a backplane. This extra x1 link is routed to
the SHB’s controlled impedance connector for use with the Chassis Plans IOB33 plug-in option card. The
IOB33 routes this x1 PCI Express link down to a physical x4 PCIe edge connector on the board. A x4
connector is used so that the IOB33 can be used on other Chassis Plans SHBs that may support a x4 PCIe
expansion link rather than a x1. The electrical width of this expansion link is determined by the board’s