Chassis Plans JXT6966, Техническое описание оборудования

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PCI Express Reference JXT6966 / JXTS6966 Technical Reference
CHASSIS PLANS 2-2
Scalability is a core feature of PCI Express. Some chipsets allow a PCI Express link to be subdivided into
additional links, e.g., a x8 link may be able to be divided into two x4 links. In addition, although a board
with a higher number of lanes will not function in a slot with a lower number of lanes (e.g., a x16 board in
a x1 slot) because the connectors are mechanically and electrically incompatible, the reverse configuration
will function. A board with a lower number of lanes can be placed into a slot with a higher number of lanes
(e.g., a x4 board into a x16 slot). The link auto-negotiates between the PCI Express devices to establish
communication. The mechanical option card slots on a PICMG 1.3 backplane must have PCI Express
configuration straps that alert the SHB to the PCI Express electrical configuration expected. The SHB can
then reconfigure the PCIe links for optimum system performance.
For more information, refer to the PCI Industrial Manufacturers Group’s
SHB Express® System Host
Board PCI Express Specification, PICMG
®
1.3
.
SHB Configurations
The JXT6966 and JXTS6966 are combo class SHBs that support either PCI Express server-class or
graphics-class backplane configurations. Server applications require multiple, high-bandwidth PCIe links,
and therefore the server-class SHB/backplane configuration is identified by multiple x8 and x4 links to the
SHB edge connectors.
SHBs which require high-end video or graphics cards generally use a x16 PCI Express link. The graphics-
class SHB/backplane configuration is identified by one x16 PCIe link and one x4 or four x1 links to the
edge connectors. As PCI Express chipsets continue to evolve, it is possible that more x4 and/or x1 links
could be supported in graphics-class SHBs. Currently, most video or graphics cards communicate to the
SHB at an effective x1, x4 or x8 PCI Express data rate and do not actually make use of all of the signal
lanes in a x16 connector.
NOTE:
The JXT6966 / JXTS6966 eliminates the PICMG 1.3 requirement that server-class SHBs should
always be used with server-class PICMG 1.3 backplanes and graphics-class SHBs should always be used
with graphics-class PICMG 1.3 backplanes. This is because the PCIe links integrated JXT processors and
SHB architecture itself can sense the backplane end-point devices and configure the SHB links for either
server or graphics-class operations. For this reason the Chassis Plans JXT6966 and JXTS6966 are called
combo-class SHBs.