Chassis Plans JXT6966, Техническое описание оборудования

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JXT6966 / JXTS6966 Technical Reference PCI Express Reference
2-1 CHASSIS PLANS
Chapter 2 PCI Express® Reference
Introduction
PCI Express
®
is a high-speed, high-bandwidth interface with multiple channels (lanes) bundled together
with each lane using full-duplex, serial data transfers with high clock frequencies.
The PCI Express architecture is based on the conventional PCI addressing model, but improves upon it by
providing a high-performance physical interface and enhanced capabilities. Whereas the PCI bus
architecture provided parallel communication between a processor board and backplane, the PCI Express
protocol provides high-speed serial data transfer, which allows for higher clock speeds. The same data rate
is available in both directions simultaneously, effectively reducing bottlenecks between the system host
board (SHB) and PCI Express option cards.
PCI Express option cards may require updated device drivers. Most operating systems that support legacy
PCI cards will also support PCI Express cards without modification. Because of this design, PCI, PCI-X
and PCI Express option cards can co-exist in the same system.
PCI Express connectors have lower pin counts than PCI bus connectors. The PCIe connectors are
physically different, based on the number of lanes in the connector.
PCI Express Links
Several PCI Express channels (lanes) can be bundled for each expansion slot, leaving room for stages of
expansion. A link is a collection of one or more PCIe lanes. A basic full-duplex link consists of two
dedicated lanes for receiving data and two dedicated lanes for transmitting data. PCI Express supports
scalable link widths in 1-, 4-, 8- and 16-lane configurations, generally referred to as x1, x4, x8 and x16
slots. A x1 slot indicates that the slot has one PCIe lane, which gives it a bandwidth of 250MB/s in each
direction. Since devices do not compete for bandwidth, the effective bandwidth, counting bandwidth in
both directions, is 500MB/s (full-duplex).
The number and configuration of an SHB’s PCI Express links is determined by specific component PCI
Express specifications. In PCI Express Gen 1 the bandwidths for the PCIe links are determined by the link
width multiplied by 250MB/s and 500MB/s, as follows:
Slot Full-Duplex
Size Bandwidth Bandwidth
x1 250MB/s 500MB/s
x4 1GB/s 2GB/s
x8 2GB/s 4GB/s
x16 4GB/s 8GB/s
In PCI Express Gen 2 the bandwidths for the PCIe links are doubled as compared to PCIe Gen 1.1 as
shown below:
Slot Full-Duplex
Size Bandwidth Bandwidth
x1 500MB/s 1GB/s
x4 2GB/s 4GB/s
x8 4GB/s 8GB/s
x16 8GB/s 16GB/s