Chassis Plans ATXP-875P, Техническое описание

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ATXP-875P Technical Reference Appendix C: Communication Devices
Chassis Plans 71
On-board Ethernet
The ATXP-875P features two 10/100/1000 Ethernet controllers. Ethernet controller 1 is an Intel 82559ER 10/1000
(or 82551ER), that may optionally be upgraded to an Intel 82540EM, which is a 10/100/1000Mbps device. The
optional Ethernet controller 2 is the Intel 82547GI 10/100/1000 Ethernet controller.
The 82559ER/551ER is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities,
which enable the 82559ER/551ER to perform high-speed data transfers over the PCI bus. The 82559ER/551ER bus
master capabilities enable the component to process high-level commands and to perform multiple operations,
thereby off-loading communication tasks from the system CPU.
It can operate in either full duplex or half duplex mode. In full duplex mode it adheres to the IEEE 802.3x Flow
Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism.
The Intel 82540EM (optional for Ethernet 1) combines Intel’s fourth-generation Gigabit MAC design, with fully
integrated, physical-layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications (802.3, 802.3u, 802.3ab).
The Intel 82540EM Gigabit Ethernet Controller architecture is optimized to deliver both high-performance
networking and PCI bus efficiency with the lowest power and smallest size. Using state logic design with a
pipelined DMA Unit and 128-bit-wide buses for the fastest performance, the 82540EM controller handles Gigabit
Ethernet traffic with low network latency and minimal internal processing overhead. The controller’s architecture
includes independent transmit and receive queues to limit PCI bus traffic, and a PCI interface that maximizes the use
of bursts for efficient bus usage. The Intel 82540EM Gigabit Ethernet Controller prefetches up to 64 packet
descriptors in a single burst for efficient PCI-bandwidth usage. A 64KB, on-chip packet buffer maintains superior
performance as available PCI bandwidth changes. Advanced interrupt moderation hardware manages interrupts
generated by the 82540EM controller to further improve system efficiency. In addition, using hardware acceleration,
the controller also offloads tasks from the host processor, such as TCP/UDP/IP checksum calculations and TCP
segmentation.
It can be enabled or disabled through jumper JP23.
The Intel® 82547GI(EI) (optional second Ethernet) Gigabit Ethernet Controller is a single, compact component with
integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. This device utilizes
the Communications Streaming Architecture (CSA) port of the 875P chipset. The Intel® 82547GI(EI) allows for a
Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100
Mbps Fast Ethernet designs. The Intel® 82547GI(EI) integrates Intel’s fourth generation gigabit MAC design with
fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE_TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting
and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer
functions, the controller utilizes dedicated CSA port capability with a theoretical bandwidth of 266 MBytes/second.
The 82547GI(EI) Gigabit Ethernet Controller with Communications Streaming Architecture is designed for high
performance and low memory latency. The CSA port architecture is invisible to both system software and the
operating system, allowing conventional “PCI-like” configuration. Wide internal data paths eliminate performance
bottlenecks by efficiently handling large address and data words. The 82547GI(EI) controller includes advanced
interrupt handling features. The 82547GI(EI) uses efficient ring buffer descriptor data structures, with up to 64
packet descriptors cached on chip. A large 40 KByte on-chip packet buffer maintains superior performance. In
addition, by using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum
calculations and TCP segmentation.
The RJ45 Ethernet Connector pin-out of Ethernet 2 can be seen on Table A-14 , and the RJ45 Ethernet Connector
(USB/RJ45 combo) pin-out of Ethernet 1 can be seen on Table A-15.