Casio SF-8350, Руководство по обслуживанию и список запасных частей

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— 15 —
14. Apply VDD to ROM.
VREG,V1~V4
Output
for LCD
drive
PDB
µ
PD3055GF002-2BA
VDD2
VDD1
VO1
GND
(Pin3)
(Pin2)
(Pin32) (Pin20)
(Pin31)
(Pin25) (Pin40)
(Pin17)
(Pin24)
(Pin35)
VIN
GND VDD VOT
LSI
MON
SWO
LSO
VOB
µ
PD65005G-452-22
KAC
KIO
ADDRESS BUS
2 MHz
VDD
ON
MAIN SWITCH
SW
GND
VDD
GND
Transistor Q1
(Pin53)
(Pin54)
(Pin41)
(Pin1)
(Pin2)
(Pin3)
2
14
15
17
CPU
VDD
EO
7
(Pin69)
"H"
"H"
"H"
16
10
VDD
ADDRESS
DATA
"H"
VDD
1
CR-2032 X 2 pcs.
Batteries
"L" "H"
(Pin22)
"L"
CE
"L"
VCC
OSCO OSCI
INIT1
(Pin70)
(Pin30)
INT0
V2ON
Gate array
"L"
VDD
DATA BUS
(Pin40) (Pin45)
(Pin36)
"L"
(Pin29)
(Pin39) (Pin30)
4
3 13
6
10-1. System chart
Generally, SF-8350 is working with the following steps.
10. Output "H" from V2ON terminal.
12. Output all LCD drive voltages.
11. Output "H" from VOT terminal.
13. Output "L" from VOB terminal.
17. CPU receives data from ROM.
16. CPU sends address to ROM.
2. Output VDD (4.5V).
1. Supply 6V to VDD1 and VDD2.
15. CPU sends ROM chip enable
signal from EO terminal.
5
OFF
10. CIRCUIT EXPLANATIONS
Open
9
8
3. Output "L" from SWO terminal.
5. Main switch ON.
6. Input "L" to SW terminal.
7. Output "L" from KAC terminal.
8. Push power on button switch.
4. Output "H" from LSO terminal.
9. CPU oscillation is generated.
12
11
ROM
(Operation program)
µ
PD23C4001EBGW-301
Power supply chip
SC371015FU