27/09/2002
V560 User Manual
23
4.12. INTERRUPT LEVEL & VETO REGISTER
(Base a %06 r/w)
This register contains the value of the interrupt level set (bit <0..2>) and the status of the VETO
latched during the last read counter operation (bit<8>). Bits <7..3> and bits <15..8> are unused and
are read as "one" on the VME data bus.
The status of the VETO is latched whenever a counting channel is read via VME;
•
VETO = 0 the module was in the inhibit state when the channel has been read.
•
VETO = 1 the module was able to count when the channel has been read.
If the module was able to count, the counter value previously read has been latched "on fly" and may
be not correct.
During word cycle the VETO value is latched during the access at the lowest addresses.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LEV<2..0>
V.
VETO
Interrupt Level
Fig. 4.7: Interrupt Level & VETO register
4.13. INTERRUPT VECTOR REGISTER
(Base a %04 r/w)
The value stored in this register is the STATUS/ID that the V560 INTERRUPTER places on the VME
data bus during the interrupt acknowledge cycle. (Bits 8 to 15 are unused and are read as "one" on
the VME data bus).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Interrupt STATUS/ID
S T A T U S / I D
Fig. 4.8: Interrupt Vector register