CAEN
Electronic Instrumentation
UM3148
–
DT5730/DT5725 User Manual rev. 2
33
Self-Trigger
Each channel is able to generate a self-trigger signal when the digitized input pulse exceeds a configurable threshold
(register address 0x1n60). The self-triggers of each couple of adjacent channels are then processed to provide out a
single trigger request. The trigger requests are propagated to the central trigger logic where they are ORed to produce
the board common trigger, which is finally distributed back to all channels causing the event acquisition (see
Fig. 9.9
).
Fig. 9.10
schematizes the self-trigger and trigger request logic having the channel 0 and channel 1 couple as an
example.
CH0
CH1
PULSE
OVTHR
Bits[1:0] of 0x1084
PULSE
OVTHR
SELF_TRG [0]
SELF_TRG [1]
AND
ONLY 0
ONLY 1
OR
Bit[2] of 0x1084
TRG_REQ [0]
Fig. 9.10:
Self Trigger and Trigger Request logic for Ch0 and Ch1 couple. A single trigger request signal is generated.
The FPGA, by register address 0x1n84, can be programmed in order the self-trigger to be:
▪
an
over/under-threshold signal
(see
Fig. 9.11
).
This signal can be programmed to be active (i.e. “1”) as long as
the input pulse is over the threshold or under the threshold (depending on the trigger polarity bit at register
address 0x8000).
CH0 IN
THRESHOLD
over-threshold signal [0]
under-threshold signal [0]
Fig. 9.11:
Channel over/under threshold signal