CAEN
Electronic Instrumentation
UM3148
–
DT5730/DT5725 User Manual rev. 2
21
PLL Mode
The Phase Detector within the AD9520 device allows to couple REF-CLK with a VCXO (500 MHz frequency) providing
out the nominal ADCs frequency (500 MHz for DT5730 and 250 MHz for DT5725); for this purpose, it is necessary that
REF-CLK is a submultiple of the VCXO frequency.
As introduced in §
Clock Distribution
, the source of the REF-CLK signal can be external (see
Fig. 9.2
) on CLK-IN front
panel connector or internal from the 50 MHz local oscillator. The following options are allowed:
1.
50 MHz internal clock source
–
It’s the standard operating mode, where the default AD95
20 configuration
doesn’t
require to be changed. OSC-CLK = REF-CLK.
2.
50 MHz external clock source
–
In this case it is not required to reprogram the AD9520 dividers, as the external
clock reference is identical to the frequency of the internal oscillator. CLK-IN = OSC-CLK = REF-CLK.
Note that, In order the board to sense the external signal on CLK-IN and use it as new reference, bit[6] at
register address 0x8100 must be set (see
[RD2]
).
3.
External clock source different from 50 MHz
–
In this case, the user is required to program the AD9520 dividers
in order to lock the VCXO to REF-CLK in order to provide out the 500 MHz (DT5730) or 250 MHz (DT5725)
nominal sampling frequency. In principle, the allowed external frequencies are submultiples of the VCXO
frequency (500 MHz). CLK-IN = REF-CLK.
Note:
the user who wants to work as in point 3, please contact CAEN indicating the required reference clock frequency
to check its feasibility and then receive the PLL programming file. T
he “Upgrade PLL” f
unction in CAENUpgrader
software tool can be used to update the digitizer PLL. See §
11
for the program description and refer to
[RD1]
for
documentation. The programming file also takes care to set the board to sense the external signal on CLK-IN.
Changing the ADC Frequency
Please, contact CAEN (see §
14
) for information on the feasibility to operate the DT5730/DT5725 with a sampling
frequency lower than the nominal.
Trigger Clock
TRG-CLK signal has a 125-MHz frequency, that is equal to
1/4
(DT5730) or
1/2
(DT5725) of SAMP-CLK. In consequence, a
4 samples (DT5730) or 2 samples (DT5725)
“uncertainty” occurs over the acquisiti
on window.