Broadcom PLX PCI 9052RDK-LITE, Справочник по аппаратуре

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4.2.4.2 Initialization Control Register
The Initialization Control Register CNTRL must be set to 0x007X0X12h where X represents the
appropriate values for the specific adapter. For PCI v2.1 compatible systems, set CNTRL[18] = 0 and
CNTRL[14] = 1, in which case CNTRL[22:19] become Don’t Cares.
4.2.4.3 Interrupt Control/Status Register
The Interrupt Control/Status Register bit (INTCSR[12]) must be set to 1 to enable ISA interface mode. If
interrupts are desired, enable the appropriate local interrupts in the INTCSR register and also enable the
PCI interrupt (INTCSR[6]).
4.2.5 Interrupts
PCI interrupt lines are allocated in a different manner to ISA interrupt lines (IRQs). On ISA cards there are
jumpers to select the appropriate IRQ for the application. In single function PCI devices there is only one
interrupt, INTA#, and it may be shared among other PCI devices. To allow the ISA card to generate PCI
interrupts, route the ISA card IRQ to one of the PCI 9052 local interrupt input (LINTix) pins. Once the
INTCSR register has been enabled, the active high assertion of the local interrupt will generate the PCI
INTA# signal.
LINTix pins should not be left floating. A pull up or pull down resistor should be used to pull the interrupt
to its inactive state and ensure that the interrupt is not generated before the driver is loaded.
4.2.6 Serial EEPROM
A serial EEPROM is required when using the PCI 9052 in ISA mode. The EEPROM must be used to set
all the local registers mentioned above. The PCI 9052 will not function in ISA mode unless a correctly
programmed EEPROM is present.
4.2.7 PCI Access to Local ISA Bus
PCIBAR 0 and 1 are the addresses of the PCI 9052 registers in the PCI memory and I/O spaces,
respectively. PCIBAR 2 and 3 are the addresses in the PCI memory and I/O spaces that are mapped to
the ISA memory and I/O spaces, respectively.
Taking the example used before:
Local address space 0 = memory mapped from 0x00001000h to 0x000013ffh
Local address space 1 = I/O mapped from 0x00000300h to 0x0000031fh
Assume that the BIOS places the following values in the PCIBARs;
PCIBAR2 = 0xffcf0000h
PCIBAR3 = 0x0000fc01h
An access to address 0xffcf0014h will then result in an access on the local bus at location 0x00001014h.
However, Windows uses virtual memory addressing. If Windows software such as PLXMon is used, then
the designer will have to know the Windows address that maps to the appropriate physical PCI address.
PLXMon provides predefined variables that tell the user the appropriate Windows address. For example,
the variable
s0 refers to Local Address Space 0. To read a byte from Local Address Space 0 with an
offset of 8 bytes from the base, type the following in the lower pane of PLXMon:
db s0 +8
A complete list of variables can be obtained by typing vars in the lower pane of PLXMon. Refer to the
PLXMon User’s Manual for more information.
The I/O space is a little more complicated. The least significant bit in PCIBAR3 is only used to show that
this location exists in I/O space. Therefore, the real base address is 0x0000fc00h, not 0x0000fc01h. In
the original example the I/O region base was lowered and the range increased because the original base
PCI 9052RDK-LITE Hardware Reference Manual v1.3
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