background image

A

A

B

B

C

C

D

D

E

E

4

4

3

3

2

2

1

1

Default: both LINTi1 and LINTi2 
are active high interrupt inputs.
Install JP3 & JP4 2-3

LCLK source selection. Fit
one resistor only

Multiplexed mode: install JP5 1-2
non-multiplexed mode: install
JP5 2-3

91-0023-002-A

002

PCI9052, Clock Circuit and E2PROM

PLX TECHNOLOGY, INC.

870 Maude Ave,   Sunnyvale, CA 94085

Custom

3

9

Friday, July 12, 2002

www.plxtech.com

Title

Size

Document Number

Rev

Date:

Sheet

of

PE

LA[27:2]

AD[31:0]

PRE

USER3/CS3#

USER2/CS2#

USER1/LLOCKo#

USER0/WAITo#

LA24

LBE3#

LD11

LD15

LD1

LW/R#

LA2

LA19

LA7

LA23

LD5

LA11

LA15

LA10

LD8

LA27

CS0#

LA12

LD3

LA9

LD9

LBE0#

LA4

LD13

LA26

CS1#

LA8

LA20

LA25

BTERM#

LA14

LD14

LBE2#

LA13

LD6

LD2

LA18

LD4

READY#

LA21

LA16

LA22

LA5

LD10

LBE1#

RD#

LD7

LD0

LA3

LD12

LA6

LA17

LD28

LD19

LD30

LD18

LD29

LD17

LD31

LD16

LD23

LD22

LD21

LD20

LD27

LD24
LD25
LD26

EEDO

EEDI

RSTL

IRDYL

EESK

INTAL

USER3/CS3#

READY#

PERRL

CS0#

LBE3#

PAR

USER1/LLOCKo#

LHOLDA

BTERM#

C/BE1L

USER2/CS2#

WR#

LOCKL

TRDYL

LINTi1

LBE1#

LBE0#

LHOLD

RD#

LW/R#

SERRL

C/BE3L

LBE2#

LD[31:0]

STOPL

ADS#

C/BE0L

LINTi2

CS1#

ALE

FRAMEL

PCLK

IDSEL

C/BE2L

MODE

BLAST#

EECS

DEVSELL

USER0/WAITo#

AD8

AD2

AD10

AD9

AD4

AD30

AD29

AD28

AD1

AD6

AD5

AD20

AD27

AD3

AD0

AD26

AD31

AD19

AD7

AD22

AD18

AD23

AD21

AD12

AD15

AD24

AD14

AD25

AD13

AD16

AD11

AD17

LD30

LD25

LD16

LD19

LD12

LD24

LD0

LD2

LD5

LD15

LD31

LD28

LD17

LD9

LD20

LD13

LD1

LD26

LD22

LD14

LD10

LD21

LD7

LD27

LD23

LD29

LD4

LD18

LD11

LD3

LD6

LD8

LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA24
LA25
LA26
LA27

LRESET
CHRDY
NOWS#

TEST

MODE

LINTi2

LINTi1

CHRDY

LCLK

LINTi1
LINTi2

WR#

ADS#
LHOLD

BLAST#

WR# 4,5

READY#

5

LW/R# 5
RD# 4,5

ALE 4,5

BTERM# 5

BLAST# 5

ADS# 5

PAR

2

INTAL

2

LOCKL

2

USER3/CS3# 4,5

USER2/CS2# 4,5

CS0# 4,5
CS1# 4,5

LBE1# 4,5
LBE2# 4,5
LBE3# 4,5

LBE0# 4,5

TEST

5

IDSEL

2

RSTL

2

PCLK

2

PERRL

2

SERRL

2

STOPL

2

DEVSELL

2

IRDYL

2

TRDYL

2

FRAMEL

2

LA[27:2]

4,5

AD[31:0]

2

LHOLD 4,5

C/BE1L

2

C/BE2L

2

C/BE0L

2

C/BE3L

2

LINTi1 5

USER1/LLOCKo# 4,5

LD[31:0]

4,5

LINTi2 5

LHOLDA 4,5
USER0/WAITo# 4,5

LRESET

4,5

CHRDY

4,5

NOWS#

4,5

BCLKo 5

LCLK

4,5

8MHZ

4,5

16MHZ

4,5

32MHZ

4,5

ISA_INT

4

CHCHK#

4,5

XINT1

4

XINT2

4

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

C25
100pF

C28

0.1uF

C29

0.1uF

JP3

HEADER 3

1
2
3

R66

10K

C32

0.1uF

C30

0.1uF

RN17

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

R31
10K

JP1

HEADER 8X2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

RN11

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

C37

0.1uF

RN12

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

C49

0.01uF

RN2

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

RN10

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

C36

0.1uF

PA4

R2

10K

JP4

HEADER 3

1
2
3

R15

4K7

R11

10K

R14

10K

R3

47R

C46

0.01uF

R1
10K

RN3

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

R59

1K

C47

0.01uF

RN6

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

C39

0.1uF

RN19

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

RN14

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

RN9

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

JP5

HEADER 3

1
2
3

C31

0.1uF

R32
10K

R17

10K

R12

10K

C42

0.01uF

C35

0.1uF

RN5

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

R16

10K

C33

0.1uF

RN8

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

R26
10K

R19

10K

RN15

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

RN4

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

C51

0.01uF

RN16

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

U6

93LC46B (8DIP-Socket)

1
2
3
4

8
7
6
5

CS
SK

DI

DO

VCC
PRE
PE
GND

RN18

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

RN13

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

PA2

R20

10K

R13
10K

PA3

C48

0.01uF

R18

10K

C44

0.01uF

C34

0.1uF

C43

0.01uF

C50

0.01uF

PA5

RN7

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

RN1

742-08-3-103-J-XX

1
2
3
4

5

6

7

8

C45

0.01uF

U2

PCI9052

43
42
39
38
37
36
35
34
32
31
30
29
28
25
24
23
11

8
7
6
5
4
3
2

157
156
155
154
153
152
151
150

92
93
94
95
96
97
98
100
101
102
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
122

91
90
89
88
87
86
85
84
83
82
79
78
77
76
75
74
73
72
71
70
69
62
61
60
59
58
57
56
55
54
53
52

49
48
47
46

123
64
127
126
125

124
129
128

130
131
140
141

63
135

134
133
138
139

137
136

132

68

33
22
12

158

159

21

149

13
16
14
15
18

17
19
20

44

148

142
144
145
143

99

1

10

27

41

50

66

81

103

121

146

9

26

40

51

65

80

104

120

147

160

45
67

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9

LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA24
LA25
LA26
LA27

LAD0
LAD1
LAD2
LAD3
LAD4
LAD5
LAD6
LAD7
LAD8
LAD9

LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
LAD16
LAD17
LAD18
LAD19
LAD20
LAD21
LAD22
LAD23
LAD24
LAD25
LAD26
LAD27
LAD28
LAD29
LAD30
LAD31

ISAA0/LBE0#
ISAA1/LBE1#

LBE2#

SBHE#/LBE3#

ADS#

BALE/ALE

LW/R

RD#

WR#

BLAST#

BTERM#

LRDYI#

MEMRD#/CS0#

MEMWR#/CS1#

USER2/CS2#
USER3/CS3#

BCLK0

LCLK

LHOLD

LHOLDA

IORD#/USER0/WAIT0#

IOWR#/USER1/LLOCK#

LINTI1
LINTI2

LRESET

MODE

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IDSEL

PAR

CLK

FRAME#
DEVSEL#
IRDY#
TRDY#
LOCK#

STOP#
PERR#
SERR#

INTA#

RST#

EECS
EESK
EEDI
EEDO

TEST

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

CHRDY

NOWS#

Содержание PLX PCI 9052RDK-LITE

Страница 1: ...PCI 9052RDK LITE Hardware Reference Manual...

Страница 2: ......

Страница 3: ...PCI 9052RDK LITE Hardware Reference Manual Version 1 3 October 2004 Website http www plxtech com Technical Support http www plxtech com support Phone 408 774 9060 800 759 3735 Fax 408 774 2169...

Страница 4: ...to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX products PLX Technology and the PLX logo are registere...

Страница 5: ...ocument describes the PLX PCI 9052RDK LITE a Rapid Development Kit from a hardware perspective It contains a description of all major functional circuit blocks on the board and also is a reference for...

Страница 6: ......

Страница 7: ...ON 15 4 1 1 Range Register 15 4 1 2 Base Address Re map Register 15 4 1 3 Chip Select Register 15 4 2 ISA REGISTER CONFIGURATION EXAMPLE 16 4 2 1 ISA Memory Mapping 16 4 2 2 ISA I O Mapping 16 4 2 3 C...

Страница 8: ...ersion 12 LIST OF TABLES Table 3 1 PCI 9052RDK LITE Default Memory Map 6 Table 3 2 Serial EEPROM Contents 7 Table 3 3 PCI 9052RDK LITE Board Prototyping Area Footprints 11 Table 3 4 Configuration Jump...

Страница 9: ...These allow designers to test simulate and debug their designs without fabricating their own boards saving considerable time and money in the development process and shortening time to market The RDK...

Страница 10: ...l bus clock 5V to 3 3V voltage regulator Six logic analyzer headers with standard HP footprint to allow easy probing of local bus signals 25x25 0 1 through hole prototyping grid 1 2 RDK Installation T...

Страница 11: ...I clock allowing the local bus to be run at an independent rate The buffered PCI bus clock output BCLKO may be connected to the local bus clock LCLK input through a 50 Ohm series resistor if desired P...

Страница 12: ...fetch counter The local bus pre fetch counter can be programmed for 0 no pre fetch 4 8 16 or Continuous Pre fetch Mode pre fetch counter turned off The pre fetched data can be used as cached data if...

Страница 13: ...PCI 9052 burst read write accesses to 128 Kbytes of SRAM provided in a 32 bit wide format An inexpensive 64 macrocell CPLD is used to generate various control signals for the RDK board While not requi...

Страница 14: ...he preprogrammed data in the EEPROM is used to configure the RDK board during boot up The data includes device and functional information for plug and play PnP PCI memory resource allocation and initi...

Страница 15: ...e 3 LAS3RR 31 16 FFF0 1Eh Local 0Ch LSW of Range for PCI to Local Address Space 3 LAS3RR 15 0 0000 1MB local address space for the RDK memory mapped ROM mapped into PCI memory space 20h Local 12h MSW...

Страница 16: ...CS0BASE 15 0 0001 As a default this CS is not active as its pin is used as an ISA bus signal The local address range is set from 00000000 to 000FFFFFh to allow correct ISA Memory space accesses 50h L...

Страница 17: ...are a few minor exceptions to ISA compatibility The PCI 9052RDK LITE board does not provide 5V to the ISA interface connector Also the PCI 9052 does not support ISA mastering nor ISA DMA operations L...

Страница 18: ...interface the PCI 9052 to the ISA bus using a small CPLD makes the RDK as flexible as possible as a development platform It performs the following functions Clock division to generate 16 MHz and 8 MHz...

Страница 19: ...8 15 16 54 pin TSOP 2 0 8mm pitch FP9 10 48 pin SSOP 2 300 wide 0 025 pitch FP23 24 20 pin SOIC wide 4 300 wide 0 05 pitch FP17 18 19 20 24 pin SSOP 2 150 wide 0 025 pitch FP21 22 44 pin TQFP 1 0 8mm...

Страница 20: ...nd the Land Socket plugged into the Minigrid Socket These sockets are available from Ironwood Electronics web site www ironwoodelectronics com BGA Device Ironwood BGA Land Socket Ironwood Minigrid Soc...

Страница 21: ...3 10 13 14 X X ROM Socket VCC Vcc 5 V Vcc 3 3 V JP6 1 2 2 3 NOWS Delay Disabled Enabled JP7 1 2 2 3 X Note 1 ISA Mode is selected by setting Jumper JP5 2 3 and programming INTCSR 12 1 in the EEPROM Th...

Страница 22: ......

Страница 23: ...address programmed into the LASxBA register must be a multiple of the appropriate range or 0 This restriction may require lowering the base address and increasing the range to ensure that both the IS...

Страница 24: ...s to be set to cover the memory mapped region in Local Address Space 0 Based on the method described in section 4 1 3 the CS0BASE register value should be 0x00001201h Similarly the CS1BASE register ha...

Страница 25: ...s a correctly programmed EEPROM is present 4 2 7 PCI Access to Local ISA Bus PCIBAR 0 and 1 are the addresses of the PCI 9052 registers in the PCI memory and I O spaces respectively PCIBAR 2 and 3 are...

Страница 26: ...sses Usually there is no conflict as ISA designs typically generate NOWS from the command strobe along with the address and the PCI 9052 command strobe assertion occurs after the first NOWS sampling f...

Страница 27: ...or pin A11 Remove any jumper connecting CS3 JP2 13 to either CSROM JP2 14 or CSRAM JP2 10 The RDK default configuration maps CS3 to the ROM socket with CS3BASE programmed for a 1 MB range starting at...

Страница 28: ...Customer Support at Address PLX Technology Inc 870 Maude Avenue Sunnyvale CA 94085 Phone 408 774 9060 800 759 3735 Fax 408 774 2169 Email USA http www plxtech com support Europe Middle East and South...

Страница 29: ...pin socket SMT FAI FP1 8 2 Samtec TSM 108 01 T DV 8x2 header dual row SMT FAI JP1 JP2 9 1 Sullins Electronics EZC49DCMN S526 49X2 ISA connector 100 straddlemount SMT Sullins 760 744 0125 J6 10 6 Samte...

Страница 30: ...pin half size Osc socket Thru hole Digi key U17 27 5 Harwin M20 9990305 3x1 header single row Thru hole Harwin JP3 JP7 28 1 Harting 9195107324 5x2 male connector IDC 10 Thru hole Harting J7 Manually i...

Страница 31: ...mable Logic PG4 ISA Interface Connector PG4 128KB SRAM 32K x 32 PG4 001 18 04 2001 First Production 002 7 08 2002 Update RN20 RN21 RN22 from 10K to 1K on sheet 4 to reflect the BOM Update the BOM and...

Страница 32: ...V VCC 3V3 VCC VCC VCC VCC 3V3 VCC T1 T45 T2 C23 10uF T3 C24 0 01uF T4 C91 10UF T5 C103 0 1uF T33 C92 10UF T6 T44 C5 0 047uF T7 C22 0 1uF T8 C14 0 01uF T9 C16 0 01uF T10 C17 0 01uF C93 10UF T11 C15 0 0...

Страница 33: ...4 5 6 7 8 9 10 11 12 13 14 15 16 RN11 742 08 3 103 J XX 1 2 3 4 5 6 7 8 C37 0 1uF RN12 742 08 3 103 J XX 1 2 3 4 5 6 7 8 C49 0 01uF RN2 742 08 3 103 J XX 1 2 3 4 5 6 7 8 RN10 742 08 3 103 J XX 1 2 3 4...

Страница 34: ...9 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 GND RESET_DRV 5V CHCHK S...

Страница 35: ...BTERM 3 LINTi2 3 LW R 3 32MHZ 3 4 USER0 WAITo 3 4 LBE0 3 4 LCLK 3 4 LBE2 3 4 BCLKo 3 LHOLD 3 4 LBE3 3 4 TEST 3 WR 3 4 USER1 LLOCKo 3 4 RD 3 4 CHRDY 3 4 ALE 3 4 CS0 3 4 LRESET 3 4 USER2 CS2 3 4 ADS 3...

Страница 36: ...PE57 PF41 PE3 PF16 PF89 PE56 PF81 PE5 PF15 PF100 PE52 PF85 PE1 PF13 PF96 PE49 PF83 FP2 84 Pin PLCC 9 8 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39...

Страница 37: ...31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PG40 PG185...

Страница 38: ...143 PH20 PH2 PH37 PH38 PH53 PH122 PH123 PH154 PH171 PH172 PH202 PH203 PH203 PH146 PH50 PH196 PH100 PH204 PH147 PH31 PH197 PH81 PH205 PH148 PH16 PH198 PH66 PH206 PH149 PH7 PH199 PH57 PH207 PH150 FP30 8...

Страница 39: ...PI27 PI46 PI153 PI28 PI17 PI151 PI61 PI130 PI147 PI126 PI77 PI72 PI66 PI145 PI166 PI84 PI5 PI124 PI8 PI124 PI58 PI44 PI125 PI94 PI23 PI126 PI73 PI12 PI127 PI62 PI10 PI128 PI60 PI40 PI129 PI90 PI22 PI...

Отзывы: