Broadcom PLX PCI 9052RDK-LITE, Справочник по аппаратуре

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4.2 ISA Register Configuration Example
Assume that the ISA card requires 1K bytes of memory space starting at address 0x1000h on the ISA
bus and 16 bytes of I/O space starting at address 0x308h.
4.2.1 ISA Memory Mapping
Starting with the memory space first, LAS0RR must be set to the inverse of the 1K bytes. 1K is 0x3ffh (if
location 0 is included), the inverse is 0xfffffc00h and this is the number to be placed into LAS0RR.
The base address required (0x1000h) is a multiple of the range so there is no need to modify it or the
range. The LAS0BA register is set to 0x00001001h - remember to set the least significant bit to 1 to
enable the local address space.
4.2.2 ISA I/O Mapping
For the I/O space things are a little more complicated. The base address in this example is not a multiple
of the range. Therefore, to ensure that the I/O space of the card is covered, reduce the base address
value and increase the range to compensate. [When migrating the design from ISA to PCI, reducing or
removing the decoding such that the base address starts at 0 would simplify the register settings and the
design considerably.]
Lower the base address to 0x300h. Therefore, the LAS1BA register must be set to 0x00000301h.
To ensure that the adapter’s I/O range is covered (0x308h to 0x317h), increase the range to 32 bytes i.e.
0x1fh. Therefore, the LAS1RR register is set to 0xffffffe1h. The least significant bit is set to map Local
Address Space 1 into I/O space.
4.2.3 Chip Select Configuration
Now set up the chip select registers. The CS0BASE register has to be set to cover the memory-mapped
region in Local Address Space 0. Based on the method described in section 4.1.3, the CS0BASE register
value should be 0x00001201h. Similarly, the CS1BASE register has to cover the I/O-mapped region set
up in Local Address Space 1. The value for CS1BASE should be 0x00000311h.
4.2.4 Other Local Settings
4.2.4.1 Bus Region Descriptor
The Bus Region Descriptor registers LAS0BRD and LAS1BRD can be used to select either 8- or 16-bit
ISA operation. For 8-bit ISA operation, the LASxBRD registers should be set to 0x00000022h; for 16-bit
ISA operation, the LASxBRD registers should be set to 0x00400022h.
If pre-fetching is not required, it can be disabled by enabling the pre-fetch counter (LASxBRD[5]=1) and
setting the counter to 0 (LASxBRD[4:3]=00b). e.g. LASxBRD should be set to 0x00000022h for 8-bit ISA
operation with pre-fetching disabled.
Pre-fetching can be used to improve the read data transfer rate, especially if this is combined with “PCI
Read No Flush mode” (CNTRL[16]=1). However, care should be taken to ensure that prefetching is only
used when reading from devices with non-volatile data - such as memory devices. If prefetching is used
when connected to devices with volatile data – such as a FIFO – then a single cycle read may result in
multiple accesses to the FIFO. This may result in the loss of data if a PCI Initiator reads from non-
sequential addresses. If there is any doubt about the volatility of the data on the ISA card then prefetching
should be disabled. By default, the PCI 9052RDK-LITE has pre-fetching disabled for accesses to ISA
Memory regions. It will never pre-fetch from ISA I/O regions.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
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© 2004 PLX Technology, Inc. All rights reserved.