Broadcom PLX PCI 9052RDK-LITE, Справочник по аппаратуре

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Read/write strobe delay and write cycle hold. Read and Write (RD# and WR#) signals can be
delayed from the beginning of a local bus cycle to allow the local bus timing to be tailored to the
requirements of specific peripherals. The Write Cycle Hold option extends the data valid time for
additional clock cycles beyond WR# strobe de-assertion.
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Local bus wait states. In addition to the LRDY# (local ready input) handshake signal for
variable wait state generation, the PCI 9052 has an internal wait state generator to allow the
local bus timing to be tailored to the requirements of specific peripherals. Wait states may be
inserted to adjust the R/W address to data, R/W data to data and R/W data to address times.
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Programmable pre-fetch counter. The local bus pre-fetch counter can be programmed for 0
(no pre-fetch), 4, 8, 16 or Continuous Pre-fetch Mode (pre-fetch counter turned off). The pre-
fetched data can be used as cached data if consecutive long-word aligned addresses are read.
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PCI Read/Write request timeout timer. The PCI 9052 has a programmable PCI Target Retry
Delay Timer, which when expired, generates a RETRY to the PCI bus.
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On-chip ISA interface logic. The PCI 9052 local bus supports single cycle reads/writes for 8- or
16-bit Memory and I/O access cycles on the ISA bus. Local Address Space 0 is used for ISA
Memory space accesses and Local Address Space 1 is used for ISA I/O space accesses.
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PCI LOCK mechanism. The PCI 9052 supports PCI target LOCK sequences. A PCI master can
obtain exclusive access to the PCI 9052 device by locking to the PCI 9052.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
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© 2004 PLX Technology, Inc. All rights reserved.