User Diagnostics in DOS: Broadcom NetXtreme II® Network Adapter User Guide
file:///C|/Users/Nalina_N_S/Documents/NetXtremeII/English/userdiag.htm[9/5/2014 3:45:19 PM]
A5
MSI
memory. A negative test is also performed to verify that when an MSI is masked, it does not write
an MSI message to host memory.
A6
Memory BIST Invokes the internal chip Built-In Self Test (BIST) command to test internal memory.
Group B: Memory Tests
B1
TXP
Scratchpad
The Group B tests verify all memory blocks of the Broadcom NetXtreme II adapter by writing
various data patterns (0x55aa55aa, 0xaa55aa55, walking zeroes, walking ones, address, etc.) to
each memory location, reading back the data, and then comparing it to the value written. The fixed
data patterns are used to ensure that no memory bit is stuck high or low, while the walking
zeroes/ones and address tests are used to ensure that memory writes do not corrupt adjacent
memory locations.
B2
TPAT
Scratchpad
B3
RXP
Scratchpad
B4
COM
Scratchpad
B5
CP
Scratchpad
B6
MCP
Scratchpad
B7
TAS Header
Buffer
B8
TAS Payload
Buffer
B9
RBUF via
GRC
B10
RBUF via
Indirect
Access
B11
RBUF Cluster
List
B12
TSCH List
B13
CSCH List
B14
RV2P
Scratchpads
B15
TBDC
Memory
B16
RBDC
Memory
B17
CTX Page
Table
B18
CTX Memory
Group C: Block Tests
C1
CPU Logic
and DMA
Interface
Verifies the basic logic functionality of all the on-chip CPUs. It also exercises the DMA interface
exposed to those CPUs. The internal CPU tries to initiate DMA activities (both read and write) to
system memory and then compares the values to confirm that the DMA operation completed
successfully.
C2
RBUF
Allocation
Verifies the RX buffer (RBUF) allocation interface by allocating and releasing buffers and checking
that the RBUF block maintains an accurate count of the allocated and free buffers.
C3
CAM Access
Verifies the content-addressable memory (CAM) block by performing read, write, add, modify, and
cache hit tests on the CAM associative memory.
C4
TPAT Cracker
Verifies the packet cracking logic block (i.e., the ability to parse TCP, IP, and UDP headers within an
Ethernet frame) as well as the checksum/CRC offload logic. In this test, packets are submitted to
the chip as if they were received over Ethernet and the TPAT block cracks the frame (identifying the
TCP, IP, and UDP header data structures) and calculates the checksum/CRC. The TPAT block results
are compared with the values expected by Broadcom NetXtreme II User Diagnostics and any errors
are displayed.
C5
FIO Register The Fast IO (FIO) verifies the register interface that is exposed to the internal CPUs.
C6
NVM Access
and Reset-
Corruption
Verifies non-volatile memory (NVM) accesses (both read and write) initiated by one of the internal
CPUs. It tests for appropriate access arbitration among multiple entities (CPUs). It also checks for
possible NVM corruption by issuing a chip reset while the NVM block is servicing data.
