62
IC Diagrams
CS4272, Codec
PIN DESCRIPTIONS
C
E
T
U
M
B
O
T
X
-
B
T
U
O
A
I
T
X
+
B
T
U
O
A
K
L
C
M
+
A
T
U
O
A
K
C
R
L
-
A
T
U
O
A
K
L
C
S
SDOUT (M/S
C
E
T
U
M
A
)
+
T
L
I
F
N
I
D
S
D
N
G
A
D
N
G
D
A
V
D
V
-
B
N
I
A
L
V
+
B
N
I
A
0
M
+
A
N
I
A
1
M
I2S/LJ
AINA-
RST
VCOM
1
2
3
4
5
6
7
1
2
8
22
23
24
25
26
27
28
9
10
11
7
1
2
1
18
19
20
13
5
1
4
1
16
28-Pin TSSOP
2.5 V to 5 V
Left and
Right Mute
Controls
∆Σ Modulator
∆Σ Modulator
Low-Latency
Anti-Alias Filter
External
Mute Control
Register / Hardware
Configuration
Internal Voltage
Reference
Internal
Oscillator
Volume
Control
Mi
xe
r
Selectable
Interpolation
Filter
Selectable
Interpolation
Filter
Reset
Left
Differential
Output
Right
Differential
Output
Switched Capacitor
DAC and Filter
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass Filter &
DC Offset Calibration
High Pass Filter &
DC Offset Calibration
PC
M Se
ri
a
l
Inte
rfac
e
/
Loo
pba
c
k
Left
Differential
Input
Right
Differential
Input
Volume
Control
L
e
ve
l T
ra
n
slator
Le
v
e
l Tra
n
s
lat
o
r
Serial
Audio
Input
Serial
Audio
Output
3.3 V to 5 V
5 V
Hardware or
I
2
C/SPI
Control Data
Switched Capacitor
DAC and Filter
BLOCK DIAGRAM
Pin Name
#
Pin Description
XTO
XTI
1,2
Crystal Connections
(
Input/Output
) - I/O pins for an external crystal which may be used to generate the
master clock.
MCLK
3
Master Clock
(
Input/Output
) -Clock source for the delta-sigma modulators.
LRCK
4
Left Right Clock
(Input/Output
) -
Determines which channel, Left or Right, is currently active on the
serial audio data line.
SCLK
5
Serial Clock
(Input/Output
) -
Serial clock for the serial audio interface.
SDOUT
(M/S)
6
Serial Audio Data Output
(
Output
)
-
Output for two’s complement serial audio data. This pin must be
pulled-up or pulled-down to select Master or Slave Mode.
SDIN
7
Serial Audio Data Input
(
Input
) - Input for two’s complement serial audio data.
DGND
8
Digital Ground
(
Input
) - Ground reference for the internal digital section.
VD
9
Digital Power
(
Input
)
-
Positive power for the internal digital section.
VL
10
Logic Power
(
Input
) - Positive power for the digital input/output interface.
M0
11
Mode Select 0
(
Input
) - In conjunction with M1, selects operating mode. Functionality is described in the
Hardware Mode Speed Configuration table.
M1
12
Mode Select 1
(
Input
) - In conjunction with M0, selects operating mode. Functionality is described in the
Hardware Mode Speed Configuration table.
I2S/LJ
13
Serial Audio Interface Select
(Input)
- Selects either the left-justified or I
2
S format for the Serial Audio
Interface.
RST
14
Reset
(
Input
) - The device enters a low power mode when this pin is driven low.
VCOM
15
Common Mode Voltage
(
Output
)
-
Filter connection for internal common mode voltage.
AINA-
AINA+
AINB+
AINB-
16,
17,
18,
19
Differential Analog Input
(
Input
)
-
The full scale differential input signals are presented to the delta-
sigma modulators. The full scale level is specified in the ADC Analog Characteristics specification table.
VA
20
Analog Power
(Input)
-
Positive power for the internal analog section.
AGND
21
Analog Ground
(
Input
) - Ground reference for the internal analog section.
FILT+
22
Positive Voltage Reference
(
Output
)
-
Positive reference voltage for the internal sampling circuits.
AMUTEC
23
Channel A Mute Control
(Output)
-
This pin is active during power-up initialization, reset, muting, when
master clock to left/right clock frequency ratio is incorrect, or power-down.
AOUTA-
AOUTA+
AOUTB+
AOUTB-
24,
25,
26,
27
Differential Analog Audio Output
(
Output
) - The full scale differential output level is specified in the
Analog Characteristics specification table.
BMUTEC
28
Channel B Mute Control
(Output)
-
This pin is active during power-up initialization, reset, muting, when
master clock to left/right clock frequency ratio is incorrect, or power-down.
Содержание T1 ToneMatch
Страница 10: ...10 Figure 2 T1 ToneMatch Audio Engine Exploded View ...
Страница 52: ...52 Figure 3 DSP PCB Top Component Layout and Etch Circuit Board Layout Diagrams ...
Страница 53: ...53 Figure 4 DSP PCB Top Component Layout and Power Layer Etch Circuit Board Layout Diagrams ...
Страница 54: ...54 Figure 5 DSP PCB Top Component Layout and Ground Layer Etch Circuit Board Layout Diagrams ...
Страница 55: ...55 Figure 6 DSP PCB Bottom Component Layout and Etch Circuit Board Layout Diagrams ...