58
PIN DESCRIPTION
N
O
I
T
C
N
U
F
D
N
A
E
M
A
N
L
O
B
M
Y
S
.
O
N
N
I
P
1
OE
3-state output enable input (active LOW)
2, 5, 6, 9, 12, 15, 16, 19
Q
0
to Q
7
3-state latch outputs
3, 4, 7, 8, 13, 14, 17, 18
D
0
to D
7
data inputs
)
V
0
(
d
n
u
o
r
g
D
N
G
0
1
)
H
G
I
H
e
v
i
t
c
a
(
t
u
p
n
i
e
l
b
a
n
e
h
c
t
a
l
E
L
1
1
V
0
2
CC
positive supply voltage
Pin configuration
Functional diagram
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the
HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
OPERATING
MODES
INPUTS
INTERNAL
LATCHES
OUTPUTS
OE LE
D
n
Q
0
to Q
7
enable and
read
register
(transparent
mode)
L
L
H
H
L
H
L
H
L
H
latch and
read register
L
L
L
L
l
h
L
H
L
H
latch register
and disable
outputs
H
H
X
X
X
X
X
X
Z
Z
IC Diagrams
74HC373, Octal D-type latch
S Q
R
Q2
Q1
100
I
pk
OscillatorC
T
Comparator
+
−
1.25 V
Reference
Regulator
1
2
3
4
5
6
7
8
Drive
Collector
I
pk
Sense
V
CC
Comparator
Inverting
Input
Switch
Collector
Switch
Emitter
Timing
Capacitor
GND
(Bottom View)
SOIC−8
D SUFFIX
CASE 751
1
8
1
Switch
Collector
Switch
Emitter
Timing
Capacitor
GND
Driver
Collector
I
pk
Sense
V
CC
Comparator
Inverting
Input
(Top View)
2
3
4
5
6
7
8
PIN CONNECTIONS
3x063
ALYWA
1
8
MC34063ADR2G, Inverting Switching Regulator
Содержание T1 ToneMatch
Страница 10: ...10 Figure 2 T1 ToneMatch Audio Engine Exploded View ...
Страница 52: ...52 Figure 3 DSP PCB Top Component Layout and Etch Circuit Board Layout Diagrams ...
Страница 53: ...53 Figure 4 DSP PCB Top Component Layout and Power Layer Etch Circuit Board Layout Diagrams ...
Страница 54: ...54 Figure 5 DSP PCB Top Component Layout and Ground Layer Etch Circuit Board Layout Diagrams ...
Страница 55: ...55 Figure 6 DSP PCB Bottom Component Layout and Etch Circuit Board Layout Diagrams ...
