ETX-CN700
Appendix 1
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INDEX#
This active-low Schmitt Trigger input signal is asserted by the disk drive when the diskette index hole is sensed.
TRK0#
This active-low Schmitt Trigger input signal is asserted by the disk drive when the head is positioned over the
outermost track.
WP#
This active-low Schmitt Trigger input signal is asserted by the disk drive when a disk is write-protected.
RDATA#
The active-low, raw-data read signal from the disk drive. Each falling edge represents a flux transition of the
encoded data.
DSKCHG#
This active-low input signal is asserted by the disk drive when the drive door has been opened.
DRV
This signal selects the floppy drive.
MOT
This active-low output activates the disk drive motor.
HDSEL#
This active-low output determines which disk drive head is active. Low = Head 0. High (open) = Head 1.
DIR#
This active-low output determines the direction of head movement (low = step-in, high = stepout).
STEP#
This active-low output signal is pulsed at a software-programmable rate to move the head during a seek
operation.
WDATA#
This active-low output is a write pre-compensated serial data stream to be written onto the selected disk drive.
Each falling edge causes a flux change on the media.
WGATE#
This active-low output enables the write circuitry of the selected disk drive.
Connector X4
IDE Signals
IDE signals are duplicated for the Primary and Secondary IDE channels. For each signal, the
first signal name is for the primary channel and the second signal name is for the secondary
channel.
PIDE_D0..15/ SIDE_D0..15
IDE Data Bus.
PIDE_A[0..2]/ SIDE_A[0..2]
IDE Address Bus.
PIDE_CS1#/ S
I
DE_CS1#
IDE Chip Select 1. This is the Chip Select 1 command output pin that enables the IDE device to watch the
Read/Write Command.
PIDE_CS3#/ SIDE_CS3#
IDE Chip Select 3. This is the Chip Select 3 command output pin that enables the IDE device to watch the
Read/Write Command.
PIDE_DRQ/ SIDE_DRQ
IDE DMA Request for IDE Master. This signal is asserted by an IDE device. It will be active-high in DMA or
Ultra-33 mode and always be inactive-low in PIO mode.
PIDED_AK#/ SIDED_AK#
IDE DACK# for IDE Master. This signal grants the IDE DMA request to begin the IDE Master Transfer in
DMA or Ultra-33 mode.
PIDE_RDY/ SIDE_RDY
IDE Ready. This is the input pin from the IDE Channel. It indicates that the IDE device is ready to terminate the
IDE command in PIO mode. The IDE device can de-assert this input to expand the IDE command if the device
is not ready. In Ultra-33 mode, this pin has different functions.
PIDE_IOR#/ SIDE_IOR#
IDE IOR# Command. This is the IOR# command output pin used to tell the IDE device to assert the Read Data
in PIO and DMA mode. In Ultra-33 mode, this pin has different functions.
