ETX-CN700
Appendix 1
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Signal Descriptions
Connector X1 (PCI-Bus, USB, Sound)
GND
Ground. All the GND pins on the ETX CN700 module should be connected to the baseboard ground plane.
VCC
+5V ±5% power supply. All VCC pins on the ETX CN700 module should be connected to the bas5V
plane.
3V
+3.3V ±5% supply voltage generated onboard the ETX module. These three pins may be used as a power supply
for external devices. The maximum permissible current drawn collectively from these pins is 500mA.
NOTE:
Do not connect 3.3V pins to an external 3.3V supply.
RSVD
These pins are reserved for future use or for manufacturing and test purposes. Do not connect external signals to
these pins.
All signals are 3.3V level PCI signals referenced to and tolerant of 5V signals. All the required PCI signal pull-
ups are integrated on the ETX CN700 board and are connected to either a 3.3V or 5V supply, as detailed in the
PCI specification. Any external PCI devices that have “5V tolerance” pins should have these pins connected to
an appropriate 5V reference voltage as per the manufacturer’s recommendation.
PCICLK1..4
PCI clock outputs for up to 4 external PCI slots or devices.
The baseboard designer should route these clocks for 1300pS total delay from the ETX CN700 connector pin to
the clock pin of the PCI device.
REQ[0..3]#
Bus Request signals for up to 4 external bus mastering PCI devices. When asserted, a PCI device is requesting
PCI bus ownership from the arbiter.
GNT[0..3]#
Grant signals to PCI Masters. When asserted by the arbiter, the requesting PCI master has been granted
ownership of the PCI bus.
AD[0..31]
PCI Address and Data Bus Lines. These multiplexed lines carry the address and data information for PCI
transactions. A Bus transaction consists of an Address phase followed by one or more Data phases.
CBE[0..3]#
PCI Bus Command and Byte Enables. Bus command and byte enables are multiplexed in these lines for address
and data phases, respectively.
PAR
Parity bit for the PCI bus. Generated as even parity across AD[31:0] and CBE[3:0]#.
SERR#
System Error. This signal reports address parity errors, data errors on special cycles or any other system error
where the result will be catastrophic.
GPERR#
Parity Error. This signal reports data parity errors on all bus transaction except special cycles.
PME#
Power management event.
LOCK#
Lock Resource Signal. This pin indicates that either the PCI master or the bridge intends to run exclusive
transfers.
DEVSEL#
Device Select. When the target device has decoded the address as its own cycle, it will assert DEVSEL#.
TRDY#
Target Ready. This pin indicates that the target is ready to complete the current data phase of a transaction.
IRDY#
Initiator Ready. This signal indicates that the initiator is ready to complete the current data phase of a
transaction.
STOP#
Stop. This signal indicates that the target is requesting that the master to stop the current transaction.