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ETX-CN700 

  

 

 

Appendix 1 

Page | 31  

 

 
 
 

Signal Descriptions 
Connector X1 (PCI-Bus, USB, Sound) 
 
GND 

Ground. All the GND pins on the ETX CN700 module should be connected to the baseboard ground plane. 

VCC 

+5V ±5% power supply. All VCC pins on the ETX CN700 module should be connected to the bas5V 
plane. 

3V 

+3.3V ±5% supply voltage generated onboard the ETX module. These three pins may be used as a power supply 
for external devices. The maximum permissible current drawn collectively from these pins is 500mA. 

NOTE:

 Do not connect 3.3V pins to an external 3.3V supply. 

RSVD 

These pins are reserved for future use or for manufacturing and test purposes. Do not connect external signals to 
these pins. 
 
All signals are 3.3V level PCI signals referenced to and tolerant of 5V signals. All the required PCI signal pull-
ups are integrated on the ETX CN700 board and are connected to either a 3.3V or 5V supply, as detailed in the 
PCI specification. Any external PCI devices that have “5V tolerance” pins should have these pins connected to 
an appropriate 5V reference voltage as per the manufacturer’s recommendation. 

PCICLK1..4 

PCI clock outputs for up to 4 external PCI slots or devices. 
The baseboard designer should route these clocks for 1300pS total delay from the ETX CN700 connector pin to 
the clock pin of the PCI device.  

REQ[0..3]# 

Bus Request signals for up to 4 external bus mastering PCI devices. When asserted, a PCI device is requesting 
PCI bus ownership from the arbiter. 

GNT[0..3]# 

Grant  signals  to  PCI  Masters.  When  asserted  by  the  arbiter,  the  requesting  PCI  master  has  been  granted 
ownership of the PCI bus.  

AD[0..31] 

PCI  Address  and  Data  Bus  Lines.  These  multiplexed  lines  carry  the  address  and  data  information  for  PCI 
transactions. A Bus transaction consists of an Address phase followed by one or more Data phases. 

CBE[0..3]# 

PCI Bus Command and Byte Enables. Bus command and byte enables are multiplexed in these lines for address 
and data phases, respectively. 

PAR 

Parity bit for the PCI bus. Generated as even parity across AD[31:0] and CBE[3:0]#. 

SERR# 

System Error. This signal reports address parity errors, data errors on special cycles or any other system error 
where the result will be catastrophic. 

GPERR# 

Parity Error. This signal reports data parity errors on all bus transaction except special cycles.

 

PME# 

Power management event. 

LOCK# 

Lock  Resource  Signal.  This  pin  indicates  that  either  the  PCI  master  or  the  bridge  intends  to  run  exclusive 
transfers. 

DEVSEL# 

Device Select. When the target device has decoded the address as its own cycle, it will assert DEVSEL#. 

TRDY# 

Target Ready. This pin indicates that the target is ready to complete the current data phase of a transaction. 

IRDY# 

Initiator  Ready.  This  signal  indicates  that  the  initiator  is  ready  to  complete  the  current  data  phase  of  a 
transaction. 

STOP# 

Stop. This signal indicates that the target is requesting that the master to stop the current transaction. 

Содержание BCT-ETX-CN700

Страница 1: ...Page 1 BCT ETX CN700 ETX Format Single Board Computer User Guide Document Reference Product User Guide Document Issue 1 4...

Страница 2: ...ry 10 Electromagnetic Compatibility 10 Quick Start 11 Assembly 12 Connector locations 12 Cooling 14 Stack Heights and Clearances 16 System Software 17 Operating System Install 17 Operating System API...

Страница 3: ...Liability In no event shall Blue Chip Technology be held liable for any loss expenses or damages of any kind whatsoever whether direct indirect incidental or consequential arising from the design or u...

Страница 4: ...io frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is...

Страница 5: ...the various connectors are located and their pin out details How to upgrade the system Bios Setup Connector Details Design Considerations Maintenance details We strongly recommend that you study this...

Страница 6: ...both read and write burst mode bus cycles and includes separate on chip code and data caches which employ a write back policy Cache is integrated within the CPU and operates at the full CPU frequency...

Страница 7: ...dual connectors and ATA 133 100 66 33 EIDE HDD quad ports dual connectors 512MB I2 C EEPROM providing non volatile storage Audio Integrated AC97 controller Line In Out Microphone In Communications Qua...

Страница 8: ...hree standard 16 bit ISA slots Board Profile 114 x 95 mm Power 5Volt only operation 5V 5 On board regulation for CPU core 3 3V General Operating Storage Temperature 20 C to 70 C Operating Temperature...

Страница 9: ...ot possible touch a suitable ground to discharge any static build up before touching the electronics This should be repeated if the handling continues for any length of time If it is necessary to remo...

Страница 10: ...ood metal to metal contact around the internal electronics Any metal back plate must be securely screwed to the chassis of the computer to ensure good metal to metal i e earth contact Metal screened c...

Страница 11: ...r operating limit of 60 C is for the board operation in free air which would equate to the air temperature inside an enclosure with the lid closed It is important to ensure that the operating temper i...

Страница 12: ...mber FX8 100S SV There are four mounting holes of 2 5mm diameter are available for securing the ETX CN700 to the host board Refer to Appendix 1 for details of the connector pin descriptions When insta...

Страница 13: ...r so the ETX CN700 will only fit on one orientation Trying to force the ETX CN700 in the wrong orientation may damage the connectors Figure 3 Align ETX CN700 connectors with the host board If the memo...

Страница 14: ...can flow through the enclosure the greater the cooling effect and the lower the temperature rise above the ambient air temperature However the volume produced by any fan will vary with the pressure a...

Страница 15: ...fitting the active solution it is necessary to spread some thermal grease to the surface of the boss which will contact the CPU Thermal grease is required as thermal pads provide less thermal conducti...

Страница 16: ...ETX area so lower height connectors are used Consequently the board to board gap is only 3mm Using the above example the overall height from the inside base of an enclosure to the top edge of the scr...

Страница 17: ...d driver for the VT8237 Southbridge device For Audio driver run the setup exe file from the Drivers SBPC ETXCN700 Audio folder Lastly for the LAN driver use Device Manager and when prompted point the...

Страница 18: ...descriptions of the main user configurable options are provided for information The following pages do not go into great depth so if you require more in depth data on particular BIOS settings please...

Страница 19: ...n menu allows the setting of Date and Time as well as providing details of IDE devices fitted to the unit Note In the Boot menu shown later SATA Channel 0 and 1 are equivalent to IDE 4 and IDE 5 respe...

Страница 20: ...bled for a summary of devices and their resources to eb shown after POST and prior to OS load Advanced Menu Picture B3 The Advanced Menu pages provide the means to customise the configuration of the E...

Страница 21: ...Sub Menu Picture B4 This sub menu allows the reservation of system resources for use with legacy ISA devices Chipset Devices Sub Menu Picture B5 The Chipset sub menu allows for PATA SATA USB Audio an...

Страница 22: ...selection of display type I O Device Configuration Picture B7 This sub menu allows for controlling the Serial Parallel and Floppy interfaces Hardware Monitor Picture B8 This sub menu shows on board v...

Страница 23: ...ISA Bridge which needs to be enabled if the host board supports ISA cards and the Onboard Watchdog Timeout Power Menu Picture B10 The Power Menu allows the user to set the state for power failure Opti...

Страница 24: ...ETX CN700 BIOS Setup Page 24 Security Menu Picture B11 The Security menu allows for BIOS and Boot passwords to be set...

Страница 25: ...one of the 8 needs to be removed from the Boot Order List by first selecting it and then typing the X key A device form the Excluded list can be added to the Boot Order list by first selecting it and...

Страница 26: ...ETX CN700 BIOS Setup Page 26 Exit Menu Picture B13 As well as offering the means to exit with and without saving settings this menu also allows for the System BIOS Default Settings to be restored...

Страница 27: ...MIC Audio 41 AD12 3 3 v 42 AUXAR Audio 43 AD13 3 3 v 44 ASVCC 5 v Audio 45 AD14 3 3 v 46 SNDL Audio 47 AD15 3 3 v 48 ASGND 49 CBE1 3 3 v 50 SNDR Audio 51 VCC 5 v 52 VCC 5 v 53 PAR 3 3 v 54 SERR 3 3 v...

Страница 28: ...v 38 MEMCS16 5 v 39 SA0 5 v 40 OSC 5 v 41 SA1 5 v 42 BALE 5 v 43 SA2 5 v 44 TC 5 v 45 SA3 5 v 46 DACK2 5 v 47 SA4 5 v 48 IRQ3 5 v 49 SA5 5 v 50 IRQ4 5 v 51 VCC 5 v 52 VCC 5 v 53 SA6 5 v 54 IRQ5 5 v 55...

Страница 29: ...3 v 39 VCC 5 v 40 VCC 5 v 41 I2CDAT 3 3 v 42 LTGIO FLM 2 5 v 3 3 v 43 I2CCLK 3 3 v 44 BLON 3 3 v 45 BIASON LP 2 5 v 3 3 v 46 DIGON 3 3 v 47 NC 48 NC 49 NC 50 NC 51 LPT FLPY 3 3 v 52 NC 53 VCC 54 GND 5...

Страница 30: ...3 3 v 43 SIDE_AK 3 3 v 44 PIDE_IRQ 3 3 v 45 SIDE_RDY 3 3 v 46 PIDE_AK 3 3 v 47 SIDE_IOR 3 3 v 48 PIDE_RDY 3 3 v 49 VCC 50 VCC 51 SIDE_IOW 3 3 v 52 PIDE_IOR 3 3 v 53 SIDE_DRQ 3 3 v 54 PIDE_IOW 3 3 v 55...

Страница 31: ...ternal bus mastering PCI devices When asserted a PCI device is requesting PCI bus ownership from the arbiter GNT 0 3 Grant signals to PCI Masters When asserted by the arbiter the requesting PCI master...

Страница 32: ...s USB0 USB0 Universal Serial Bus Port 0 These are the serial differential data pairs for USB Port 0 USB0 positive signal USB0 negative signal USB1 USB1 Universal Serial Bus Port 1 These are the serial...

Страница 33: ...mory read cycles to addresses below 1MB MEMW MEMW instructs memory devices to store the data present on the data bus MEMW is active for all memory write cycles SMEMW SMEMW instructs memory devices to...

Страница 34: ...duty cycle of 40 60 percent The frequency supplied by different CPU modules may vary This signal is supplied at all times except when the CPU module is in sleep mode OSC OSC is supplied by the CPU mod...

Страница 35: ...lement of 1st LVDS0 1st LVDS1 1st LVDS1 As above link1 1st LVDS2 1st LVDS2 As above link2 1st LVDS3 1st LVDS3 As above link2 1st LVDSCLK 1st LVDSCLK As above clock link 2nd LVDS0 2nd LVDS0 2nd LVDS Ch...

Страница 36: ...nels FLM First Lime Marker This output supplies the vertical synchronisation pulse for flat panels DE Data enable signal Usage depends on display type SHCLK Panel data clock signal DETECT Panel hot pl...

Страница 37: ...e the printer data into the printer AFD This active low output tells the printer to automatically feed the next single line after each preceding line has been printed PD 0 7 This bi directional parall...

Страница 38: ...t enables the write circuitry of the selected disk drive Connector X4 IDE Signals IDE signals are duplicated for the Primary and Secondary IDE channels For each signal the first signal name is for the...

Страница 39: ...an external 1 1 1 1 transformer TXD TXD ANALOG TWISTED PAIR Ethernet Transmit Differential Pair These pins transmit the serial bit stream on the Unshielded Twisted Pair UTP cable The current driven d...

Страница 40: ...rder for this pin to function 5V_SB must be supplied to the ETX module Power management signals In order for these pins to function while VCC is powered down 5V_SB must be supplied to the ETX module N...

Страница 41: ...ces only Data rate is approximate 1 10kHz This interface is intended for support of EEPROMs and other simple I O devices SMBDATA SMBCLK System Management Bus clock and data lines May be used to suppor...

Страница 42: ...ils singleboardcomputer bluechiptechnology co uk The type of information that can be made available is as follows 3D Models formats available Pro E STP IGES Dimension Drawings DWG DXF BCT Eval Schemat...

Страница 43: ...ETX CN700 Appendix 3 Page 43 System Resources Direct Memory Access Interrupt Request Memory...

Страница 44: ...ETX CN700 Appendix 3 Page 44 Input Output...

Страница 45: ...be necessary to replace the battery if present on the host carrier board if it cannot maintain the CMOS clock whilst the AC power is disconnected Once fitted inside a System Unit the servicing routin...

Страница 46: ...orrected LVDS3 pin definition on connector X3 Contact Details Blue Chip Technology Ltd Chowley Oak Tattenhall Chester CH3 9EX U K Telephone 44 0 1829 772000 Facsimile 44 0 1829 772001 www bluechiptech...

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