ETX-CN700
Appendix 1
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Connector X3
VGA Signals
HSYNC
Horizontal Sync: This output supplies the horizontal synchronization pulse to the CRT monitor.
VSYNC
Vertical Sync: This output supplies the vertical synchronization pulse to the CRT monitor.
Red, Green, Blue
Red, green and blue analog video output signals for CRT monitors. These lines should be terminated with 75
ohms to ground at the video connector.
DDCK, DDDA
These two pins can be used for a DDC interface between the graphics controller chip and the CRT monitor.
LVDS Flat Panel Interface Signals
NOTE
: The ETX CN700.module is available with either LVDS or 18 bit direct drive LCD STN/TFT interface.
This option must be specified at the time of purchase. The ETX CN700 does not support 24 bit panels in either
LVDS or direct drive LCD options
1
st
LVDS0, 1
st
LVDS0#
1st LVDS Channel, link0 differential pairs LCD data output. These signals are differential and should be routed
as differential pairs. 1
st
LVDS0# is the complement of 1
st
LVDS0.
1
st
LVDS1, 1
st
LVDS1#
As above, link1.
1
st
LVDS2, 1
st
LVDS2#
As above, link2.
1
st
LVDS3, 1
st
LVDS3#
As above, link2.
1
st
LVDSCLK, 1
st
LVDSCLK#
As above, clock link.
2
nd
LVDS0, 2
nd
LVDS0#
2nd LVDS Channel, link0 differential pairs LCD data output. These signals are differential and should be routed
as differential pairs. 2
nd
LVDS0# is the complement of 2
nd
LVDS0.
2
nd
LVDS1, 2
nd
LVDS1#
As above, link1.
2
nd
LVDS2, 2
nd
LVDS2#
As above, link2.
2
nd
LVDS3, 2
nd
LVDS3#
As above, link2.
2
nd
LVDSCLK, 2
nd
LVDSCLK#
As above, clock link.
Single channel LVDS link is use the first channel only. Dual channel links, which are commonly used to
transmit higher data rates, will use both the first and second channels.
The Txout3 and Txout3# for both first and second channels are not supported by the ETX CN700 board.
PIN NAME
LVDS SIGNAL
CHANNEL
1
st
LVDS0#
Txout0#
first
1
st
LVDS 0
Txout0
first
1
st
LVDS1#
Txout1#
first
1
st
LVDS 1
Txout1
first
1
st
LVDS2#
Txout2#
first
1
st
LVDS 2
Txout2
first
1
st
LVDS3#
Txout3#
first
1
st
LVDS 3
Txout32
first
1
st
LVDSCLK#
Txclock#
first
1
st
LVDSCLK
Txclock
first
2
nd
LVDS0#
Txout0#
second
2
nd
LVDS0
Txout0
second
2
nd
LVDS1#
Txout1#
second
2
nd
LVDS1
Txout1
second
2
nd
LVDS2#
Txout2#
second
