INTRODUCTION
I-E96-209A
2 - 1
SECTION 2 - DESCRIPTION AND OPERATION
INTRODUCTION
This section explains the functions, module circuitry, data and
connections for the Logic Master Module (IMLMM02). It also
details the function codes available to configure an LMM.
FUNCTIONAL OPERATION
The logic master module consists of six major sections. They
are Memory, Module Bus Interface, Machine Fault Timer, Slave
Expander Bus Interface, Digital Inputs/Outputs, and the
Microprocessor, Timing and Control section. See Figure
Microprocessor, Timing, and Control Circuitry
The logic master module uses a 68B09E microprocessor inte-
grated circuit operating at two megahertz. Based on the pro-
gram in ROM and the configuration in NVRAM, the processor
controls the functions of the I/O circuitry, slave expander bus
and module bus communication, as well as performing
onboard checks to verify internal integrity. Additional circuitry
provides the proper timing and clocks to run the processor and
other functions.
Module Bus Interface
The module bus interface on the logic master module allows it
to communicate with other INFI 90 modules in the same PCU.
Every module on the module bus has a unique address that
Figure 2-1. Logic Master Module Block Diagram
P1
P3
P2
TP21031A
SLAVE EXPANDER
BUS INTERFACE
DIGITAL INPUT/
OUTPUT
MODULE BUS
INTERFACE
MACHINE FAULT
TIMER
MEMORY
MICROPROCESSOR,
TIMING AND
CONTROL CIRCUITRY
