Axcera INNOVATOR, Инструкция по эксплуатации

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UHF Analog Driver/Transmitter/ Chapter 4, Circuit Descriptions
Translator
LX Series, Rev. 3 4-5
the circuitry that generates an
amplitude-modulated vestigial sideband
visual IF signal output that is made up of
the baseband video input signal (.5 to 1
Vpk-pk) modulated onto a 45.75 MHz IF
carrier frequency. The visual IF signal
and the aural IF signal are then
combined in the diplexer circuit to
produce the visual IF + aural IF output,
“G”, that is connected to J41C pin 28C
the Combined IF output of the board.
4.2.1.6 Main Video Signal Path
(Part 1 of 2)
The baseband video input connects to the
board at J41A pins 19A (-), “W”, and 20A
(+), “V”. The +, “V” and -, “W”, video
inputs are fed to Diodes CR1 to CR4 that
form a voltage-limiter network in which,
if the input voltages exceed the supply
voltages for U2B, the diodes conduct,
preventing damage to U2B. CR1 and CR3
conduct if the input voltage exceeds the
negative supply and CR2 and CR4
conduct if the input voltage exceeds the
positive supply voltage. The baseband
video input connects to the non-inverting
and inverting inputs of U2B, a differential
amplifier that minimizes any common-
mode problems that may be present on
the incoming signal
The video output of U2B is connected
through the Video Gain pot R42,
accessed through the front panel, to the
amplifier U2A. The output of U2A
connects to the delay equalizer circuits
4.2.1.7 Delay Equalizer Circuits
The delay equalizer circuits provide a
delay to the video signal, correction to
the frequency response, and
amplification of the video signal.
The video output of U2A is wired to the
first of four delay-equalizing circuits that
shape the video signal to the FCC
specification for delay equalization or to
the shape needed for the system. The
board has been factory-adjusted to this
FCC specification and should not be
readjusted without the proper equipment.
Resistors R53, R63, R61, and R58 adjust
the sharpness of the response curve while
inductors GD1, GD2, GD3, and GD4 adjust
the position of the curve. The group
delayed video signal at the output of U3A
is split with a sample connected to J8 on
the board that can be used for testing
purposes of the Post Video Delay signal.
The other portion of the video signal
connects through the Jumper W5 on J9
pins 2 and 3. The video is slit with one
part connecting to a sync tip clamp circuit
and the other part to the main video
output path through R44. A sample of the
video at “P” connects to U32 and U33 that
provides a zero adjust and a 1 Volt output
level, which connects at “T” to J41A pin 3A.
This video level is wired to the
Control/Power Supply assembly.
4.2.1.8 Sync Tip Clamp Circuit
The automatic sync tip clamp circuit is
made up of U6A, Q8, U5C, and associated
components. The circuit begins with a
sample of the clamped video that is
buffered by U3A, and is split off from the
main video path that connects to U6A. The
level at which the tip of sync is clamped is
-1.04 VDC as set by the voltage-divider
network, R77, R78, R75, R76 and R80
connected to U6A. If the video level
changes, the sample applied to U6A
changes. The voltage from the clamp
circuit that is applied to the summing
circuit at the base of Q8 will change; this
will bring the sync tip level back to -1.04
VDC. Q8 will be turned off and on
according to the peak of sync voltage level
that is applied to U6A. The capacitors C35
and C24, in the output circuit of Q8, will
charge or discharge to the new voltage
level. This will bias U5C more or less,
through the front panel MANUAL/AUT O
CLAMP switch, SW1, when it is in the Auto
Clamp-On position, between pins 2 and 3.
In AUTO CLAMP, U5C will increase or
decrease its output, as needed, to bring
the peak of sync back to the correct level.
The voltage level is applied through U5C to
U2A. In the Manual CLAMP position, SW1