ZedBoard Booting and Configuration Guide
ISE Design Suite 14.1
3
Hardware Design Block Diagram
The hardware platform for this guide is based on the Processor System (PS) configuration
and Programmable Logic (PL) bitstream described in the ZedBoard: Zynq-7000 EPP
Concepts, Tools, and Techniques hands-on guide found at
www.zedboard.org/design
.
The following figure shows a high-level block diagram of the hardware design. The
design requires:
Z7020 Zynq-7000 AP SoC
512MB DDR3 SDRAM
256Mbit QSPI Flash
USB UART Bridge Serial Port
LEDs and push button switches
Timer
Figure 1 – Reference Design Block Diagram
