12
22 Sept 2016
v1.1
2.4 Clocks
Clock synthesizer IC - U13
IDT-242 I2C ADDR:
0xD8
The FMC2 contains an IDT 8T49N242-006 I2C programmable clock synthesizer to offer
maximum clocking flexibility. Upon power up the part is configured via U14, a 24AA025T
EEPROM. A 38.888MHz crystal is used for the synthesizer’s input for optimum performance
and frequency selection. See the below figure for topology. There is also a non-populated
header (J14) available on the board. See section
The synthesizer is wired to provide 2 outputs – Q3 single ended and Q2 differential. Both Q2
and Q3 outputs are synthesized from one of three clock inputs: 38.888MHz, FMC_GBTCLK, or
PCIe_CLK. The choice of how U13 handles the input and output clocks is configured in U14.
1) Channel Q3 output – Single ended output from 1 MHz to 200 MHz on SOM Bank 13
MRCC pin (PL_CLK JX3.73).
2) Channel Q3 INV output: tied to test pad TP31.
3) Channel Q2 output is a differential output derived from either the FMC clock or the
PCIe clock and drives the SOMs MGT1 bank. The choice of which clock to use is
configured in U14, the configuration EEPROM.
4) The PCIe clock input is routed to the synthesizer and the JX3 connector in a multidrop
LVDS (M-LVDS) configuration for optimal performance.
•
Synthesizer base default address:
0xD8
•
Base address adjustable via JT1 and JT2.
For more information on the IDT 8T49N242 IC please refer to the IDT datasheet:
Figure 5 – Clock Synthesizer topology
