ATX MB-i965Q, Руководство пользователя

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BIOS
Checkpoint Description
03
Dsable NMI, Party, vdeo for EGA, and DMA controllers.
Intalze BIOS, POST, Runtme data area. Also ntalze BIOS
modules on POST entry and GPNV area. Intalzed CMOS as
mentoned n the Kernel Varable "wCMOSFlags."
04
Check CMOS dagnostc byte to determne f battery power
s OK and CMOS checksum s OK. Verfy CMOS checksum
manually by readng storage area.
If the CMOS checksum s bad, update CMOS wth power-on
default values and clear passwords. Intalze status regster A.
Intalzes data varables that are based on CMOS setup
questons.
Intalzes both the 829 compatble PICs n the system.
0
Intalzes the nterrupt controllng hardware (generally PIC)
and nterrupt vector table.
06
Do R/W test to CH-2 count reg. Intalze CH-0 as system
tmer. Install the POSTINTCh handler. Enable IRQ-0 n PIC
for system tmer nterrupt.
Traps INTCh vector to "POSTINTChHandlerBlock."
07 Fxes CPU POST nterface callng ponter.
08
Intalzes the CPU. The BAT test s beng done on KBC.
Program the
keyboard controller command byte s beng done after Auto
detecton of KB/MS usng AMI KB-.
C0 Early CPU Int Start -- Dsable Cache - Int Local APIC
C Set up boot strap processor Informaton
C2 Set up boot strap processor for POST
C Enumerate and set up applcaton processors
C6 Re-enable cache for boot strap processor
The POST code checkponts are the largest set of checkponts durng
the BIOS pre-boot process. The followng table descrbes the type of
checkponts that may occur durng the POST porton of the BIOS
(Note)
:
POST Code Checkpoints