Atmel SMART SAMA5D3 Series, Руководство пользователя

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SAMA5D3 Xplained [USER GUIDE]
Atmel-11269D-ATARM-SAMA5D3-Xplained-XPLD-User Guide_07-Sep-15
54
Figure 4-43. DDR2 Memory
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
DDR_VREF
DDR_A8
DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D15 DDR_D14
DDR_A1 DDR_A9 DDR_A2
DDR_D2
DDR_A10 DDR_A3 DDR_A11 DDR_A4 DDR_A12 DDR_A5
DDR_D1
DDR_VREF
DDR_D0
DDR_A6
DDR_D4 DDR_D3
DDR_A7
DDR_D6 DDR_D5 DDR_D7 DDR_D8
DDR_A0
DDR_A8
DDR_D27 DDR_D26 DDR_D25 DDR_D31 DDR_D29 DDR_D28 DDR_D30
DDR_A1 DDR_A9 DDR_A2 DDR_A10
DDR_D18
DDR_A3 DDR_A11 DDR_A4 DDR_A12 DDR_A5
DDR_VREF
DDR_D17 DDR_D16
DDR_A6
DDR_D19 DDR_D20 DDR_D22
DDR_A7
DDR_D23 DDR_D21 DDR_D24
DDR_A0
DDR_DQM0 DDR_DQS1 DDR_DQS0 DDR_CS DDR_BA0 DDR_BA1 DDR_BA2 DDR_CKE DDR_WE DDR_CLK DDR_RAS DDR_CLKN DDR_CAS
DDR_DQM2 DDR_DQS2 DDR_DQS3 DDR_CS DDR_BA0 DDR_BA1 DDR_BA2 DDR_WE DDR_CKE DDR_RAS DDR_CLK DDR_CAS DDR_CLKN
DDR_A13 DDR_DQM1
DDR_DQM3 DDR_A13
DDR_A13
DDR_DQM2 DDR_DQM3 DDR_DQS1 DDR_DQS0
DDR_D12 DDR_D13 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_A12 DDR_D26 DDR_D27 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25
DDR_DQS3 DDR_DQS2
DDR_D30 DDR_D31 DDR_D28 DDR_D29
DDR_BA0 DDR_BA1 DDR_BA2
DDR_A1
DDR_CKE DDR_CLK DDR_CLKN
DDR_A0 DDR_A2 DDR_A3
DDR_RAS DDR_CAS
DDR_VREF
DDR_A4 DDR_A5 DDR_A6
DDR_CS DDR_WE
DDR_A8 DDR_A9 DDR_A10 DDR_A11
DDR_DQM0 DDR_DQM1
DDR_A7
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
DDR_A[0..13]
DDR_D[0..31]
DDR_A[0..13]
DDR_D[0..31]
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A A
RevA
6 11
A
XX-XXX-XX
PPn
XXX
SAMA5D3x-II & DDR2
27-Sep-13
SAMA5D3 Xplained
19-Feb-14
Embest
XXX
XX-XXX-XX
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A A
RevA
6 11
A
XX-XXX-XX
PPn
XXX
SAMA5D3x-II & DDR2
27-Sep-13
SAMA5D3 Xplained
19-Feb-14
Embest
XXX
XX-XXX-XX
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A A
RevA
6 11
A
XX-XXX-XX
PPn
XXX
SAMA5D3x-II & DDR2
27-Sep-13
SAMA5D3 Xplained
19-Feb-14
Embest
XXX
XX-XXX-XX
DDR2 SDRAM
Address, control and data traces may not exceed 1.3 inches (33.0 mm). Address, control and data traces must be length-matched to within 0.1 inch (2.54mm). Address, control and data traces must match the data group trace lengths to within 0.25 inches (6.35mm). Keep nets as short as possible, therefore, DDR2 devices have to be placed close as possible of SAMA5D36 The layout EBI DDR2 should use controlled impedance traces of ZO= 50ohm characteristic impedance.
Differencial 100 Ohms Top/Bottom
Differencial 100 Ohms Top/Bottom
Differencial 100 Ohms Top/Bottom
C98 100nF C98 100nF
C99
100nF
C99
100nF
C73
100nF
C73
100nF
C100 100nF C100 100nF
R46 1.5K 1% R46 1.5K 1%
C68
100nF
C68
100nF
R45 1R R45 1R
R39
4.7K
R39
4.7K
R43
200R 1%
R43
200R 1%
C93
100nF
C93
100nF
C90
100nF
C90
100nF
C69
100nF
C69
100nF
R41
4.7K
R41
4.7K
C91
100nF
C91
100nF
C70
100nF
C70
100nF
C97
100nF
C97
100nF
MT47H64M16HR
DDR2 SDRAM
MN5
MT47H64M16HR
DDR2 SDRAM
MN5
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
BA0
L2
ODT
K9
DQ0
G8
DQ1
G2
DQ2
H7
DQ3
H3
DQ4
H1
DQ5
H9
DQ6
F1
DQ7
F9
UDQS
B7
UDQS
A8
LDM
F3
VDD
J9
VDD
M9
VDDL
J1
VREF
J2
VDDQ
E9
VSS
A3
VSS
E3
VDDQ
A9
VDD
E1
RFU1
A2
RFU2
E2
CKE
K2
CK
J8
CK
K8
CAS
L7
RAS
K7
WE
K3
CS
L8
VDDQ
C3
VDDQ
C7
VDDQ
C9
VSSQ
D8
VSSQ
E7
VSSQ
F2
VSSQ
F8
VDD
A1
VSS
J3
A11
P7
BA1
L3
A12
R2
BA2
L1
VSS
N1
VSSDL
J7
VSSQ
B2
RFU3
R3
DQ8
C8
DQ9
C2
DQ10
D7
DQ11
D3
DQ12
D1
DQ13
D9
DQ14
B1
DQ15
B9
VDD
R1
VDDQ
G1
VDDQ
G7
VDDQ
G9
VSS
P9
VSSQ
D2
VSSQ
A7
VSSQ
B8
VSSQ
H2
VSSQ
H8
VDDQ
G3
VDDQ
C1
UDM
B3
LDQS
E8
LDQS
F7
RFU4
R7
A13
R8
R40
4.7K
R40
4.7K
C79
100nF
C79
100nF
R36
DNP(1K)
R36
DNP(1K)
C71
100nF
C71
100nF
R47 1.5K 1% R47 1.5K 1%
R42
4.7K
R42
4.7K
MT47H64M16HR
DDR2 SDRAM
MN4
MT47H64M16HR
DDR2 SDRAM
MN4
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
BA0
L2
ODT
K9
DQ0
G8
DQ1
G2
DQ2
H7
DQ3
H3
DQ4
H1
DQ5
H9
DQ6
F1
DQ7
F9
UDQS
B7
UDQS
A8
LDM
F3
VDD
J9
VDD
M9
VDDL
J1
VREF
J2
VDDQ
E9
VSS
A3
VSS
E3
VDDQ
A9
VDD
E1
RFU1
A2
RFU2
E2
CKE
K2
CK
J8
CK
K8
CAS
L7
RAS
K7
WE
K3
CS
L8
VDDQ
C3
VDDQ
C7
VDDQ
C9
VSSQ
D8
VSSQ
E7
VSSQ
F2
VSSQ
F8
VDD
A1
VSS
J3
A11
P7
BA1
L3
A12
R2
BA2
L1
VSS
N1
VSSDL
J7
VSSQ
B2
RFU3
R3
DQ8
C8
DQ9
C2
DQ10
D7
DQ11
D3
DQ12
D1
DQ13
D9
DQ14
B1
DQ15
B9
VDD
R1
VDDQ
G1
VDDQ
G7
VDDQ
G9
VSS
P9
VSSQ
D2
VSSQ
A7
VSSQ
B8
VSSQ
H2
VSSQ
H8
VDDQ
G3
VDDQ
C1
UDM
B3
LDQS
E8
LDQS
F7
RFU4
R7
A13
R8
C94
100nF
C94
100nF
C78
100nF
C78
100nF
C74
100nF
C74
100nF
C101 4.7uF C101 4.7uF
R38
0R
R38
0R
R44 200R 1% R44 200R 1%
C95
100nF
C95
100nF
C75
100nF
C75
100nF
TP3 SMD TP3 SMD
L16
10uH
60mA
L16
10uH
60mA
C96
100nF
C96
100nF
R37
0R
R37
0R
C102 100nF C102 100nF
MN2F SAMA5D3x_BGA324 MN2F SAMA5D3x_BGA324
DDR_CAS
A5
DDR_A13
A6
DDR_A11
A7
DDR_A7
A8
DDR_A2
A9
DDR_D30
A10
DDR_D27
A11
DDR_CLKN
A12
DDR_DQSN3
A13
DDR_D25
A14
DDR_D24
A15
DDR_DQSN2
A17
DDR_D19
A18
DDR_WE
B5
DDR_BA1
B6
DDR_CKE
B7
DDR_A9
B8
DDR_A4
B9
DDR_A0
B10
DDR_D28
B11
DDR_CLK
B12
DDR_DQS3
B13
DDR_D23
B14
DDR_DQM2
B15
DDR_D16
B16
DDR_DQS2
B17
DDR_D17
B18
DDR_CS
C8
DDR_A8
C10
DDR_A1
C11
DDR_CALN
C12
DDR_VREF
C13
DDR_BA0
E9
DDR_DQSN0
D18
DDR_D12
D17
DDR_D14
D16
DDR_D22
D15
DDR_DQM3
D12
DDR_A3
D11
DDR_A6
D10
DDR_A12
D9
DDR_D13
C18
DDR_D15
C17
DDR_D20
C16
DDR_D18
C15
DDR_D21
C14
DDR_A5
E10
DDR_D31
E11
DDR_D26
E12
DDR_CALP
E13
DDR_BA2
F9
DDR_A10
F11
DDR_D29
F12
DDR_D8
F16
DDR_D6
F17
DDR_DQSN1
F18
DDR_RAS
G11
DDR_DQM0
G12
DDR_D10
G14
DDR_D7
G15
DDR_D4
G16
DDR_D3
G17
DDR_DQS1
G18
DDR_D0
H12
DDR_D2
H13
DDR_D5
H15
DDR_D1
H17
DDR_DQM1
E15
DDR_D11
E16
DDR_D9
E17
DDR_DQS0
E18
C88
100nF
C88
100nF
C80
100nF
C80
100nF
C89
100nF
C89
100nF
C82
100nF
C82
100nF
R35
DNP(1K)
R35
DNP(1K)
C66
100nF
C66
100nF
C83
100nF
C83
100nF
C81
100nF
C81
100nF
C84
100nF
C84
100nF
C76
100nF
C76
100nF
C104 100nF C104 100nF
C86
100nF
C86
100nF
C85
100nF
C85
100nF
C77
100nF
C77
100nF
C67
100nF
C67
100nF
C87
100nF
C87
100nF
C92
100nF
C92
100nF
C72
100nF
C72
100nF
C103 4.7uF C103 4.7uF
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