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SAMA5D3 Xplained [USER GUIDE]
Atmel-11269D-ATARM-SAMA5D3-Xplained-XPLD-User Guide_07-Sep-15
4.3.3
USB Type A Dual Port
Figure 4-30.
USB Type A Dual Port J19
5
TDI Test Data Input - Serial data
output line, sampled on the rising
edge of the TCK signal.
JTAG data input of target CPU. It is recommended that this pin is pulled
to a defined state on the target board. Typically connected to TDI on
target CPU.
6
GND
Common ground.
7
TMS Test Mode Select.
JTAG mode set input of target CPU. This pin should be pulled up on the
target. Typically connected to TMS on target CPU. Output signal that
sequences the target's JTAG state machine, sampled on the rising edge
of the TCK signal.
8
GND
Common ground.
9
TCK Test Clock - Output timing
signal, for synchronizing test logic
and control register access.
JTAG clock signal to target CPU. It is recommended that this pin is pulled
to a defined state on the target board. Typically connected to TCK on
target CPU.
10
GND
Common ground.
11
RTCK - Input Return Test Clock
signal from the target.
Some targets must synchronize the JTAG inputs to internal clocks. To
fulfill this requirement, a returned and resynchronized TCK can be used
to dynamically control the TCK rate. SAM-ICE supports adaptive
clocking which waits for TCK changes to be echoed correctly before
making further changes. Connect to RTCK if available, otherwise to
GND.
12
GND
Common ground.
13
TDO JTAG Test Data Output -
Serial data input from the target.
JTAG data output from target CPU. Typically connected to TDO on target
CPU.
14
GND
Common ground
15
nSRST RESET
Active-low reset signal. Target CPU reset signal.
16
GND
Common ground
17
RFU
This pin is not connected.
18
GND
Common ground
19
RFU
This pin is not connected.
20
GND
Common ground
Table 4-16.
JTAG/ICE Connector J24 Signal Descriptions (Continued)
Pin
Mnemonic
Signal Description
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