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AVR1306 

8045A-AVR-02/08 

 Timer 

overflow. 

  Timer error (Input capture data lost because input capture buffer is full). 

  Compare or capture. Separate interrupts for each channel. 

3.4 Period Setting 

Each TC module has a period register (PER[H:L]) that controls the TOP value of the 
counter (except in frequency generation mode).  

The PER[H:L] register is double buffered through the PERBUF[H:L] register. Double 
buffered registers are covered in section 3.7

The PER[H:L] register is automatically initialized to 0xFFFF after a reset. 

3.5 Capture or Compare Channels 

Each TC module has two or four capture or compare channels. The channels can be 
set up for either input capture or compare match. It is not possible to use the same 
TC module for both input capture and compare match at the same time. Input capture 
can be used to time stamp event, measuring waveform parameters like frequency or 
duty cycle. The compare match feature can be used to generate interrupts or events 
at certain time points, or for PWM/waveform generation.  

The compare or capture channels consist of a set of 16-bit registers named CCx[H:L], 
where x indicates the channel. Timer0, with 4 channels, has CCA[H:L], CCB[H:L], 
CCC[H:L] and CCD[H:L], while Timer1 has CCA[H:L] and CCB[H:L]. In addition, each 
CCx[H:L] register has an associated buffer register CCxBUF[H:L]. Double buffered 
registers are covered in detail in section 3.7

When used for input capture, the value of the PER register determines how input 
capture values are interpreted. If bit 15 of PER is set to one, the entire 16 bit counter 
value is stored in the capture buffer. If bit 15 of PER is zero, the event polarity is 
stored in bit 15 in the capture buffer. This can be used to measure frequency 
parameters like duty cycle using only one input pin and one capture channel. 

3.6 Event Input Selection 

The TC input capture system uses the XMEGA event system to trigger an input 
capture. Refer to application note AVR1001 for more information about the XMEGA 
event system. 

When the TC is used for input capture, all enabled input capture channels must be 
associated with an event channel. The EVSEL[3:0] bits of the CTRLD register select 
the event channels that are associated with the input capture channels. EVSEL3 must 
be 1 to select an event source. EVSEL[2:0] selects between the 8 event channels.  

The event channels associated with the different channels cannot be selected 
individually. Table 3-2 shows the mapping between global event channels and input 
capture channels when EVSEL3 = 1 and EVSEL[2:0] = N. The “%” is the modulo 
operator. Note that when a set of event channels have been selected for the TC, this 
does not mean that these event channels are used exclusively by the TC. The TC 
simply “listens” to the selected channels and is able to receive events on these event 
channels. 

 

Содержание AVR1306

Страница 1: ...ch Timer 1 Double buffered 32 bit operation with 32 bit input capture by timer cascading Event counter Timer overflow and error interrupts and events Input capture interrupts and events 1 Introduction...

Страница 2: ...to I O pin Typical applications include Timing Periodic interrupt event generation Pulse Width Modulation Event time stamping Event counting Signal parameter measurements Period duty cycle etc 3 1 Tim...

Страница 3: ...ed TC_CSEL_DIV1_gc fCLK SYS TC_CSEL_DIV2_gc fCLK SYS 2 TC_CSEL_DIV4_gc fCLK SYS 4 TC_CSEL_DIV8_gc fCLK SYS 8 TC_CSEL_DIV64_gc fCLK SYS 64 TC_CSEL_DIV256_gc fCLK SYS 256 TC_CSEL_DIV1024_gc fCLK SYS 102...

Страница 4: ...ister CCxBUF H L Double buffered registers are covered in detail in section 3 7 When used for input capture the value of the PER register determines how input capture values are interpreted If bit 15...

Страница 5: ...h buffer register has a related buffer valid flag in the CTRLE register The buffer valid flag is set when a new value is written to the corresponding buffer register The flag is cleared when the buffe...

Страница 6: ...the counter value while the counter is running is allowed The write access has higher priority than count clear or reload and will be immediate However if the value written is outside the BOTTOM TOP...

Страница 7: ...s Figure 3 4 shows in this mode of operation the counter counts from BOTTOM to TOP then restarts from BOTTOM The waveform generator output is set on the compare match between the count and compare reg...

Страница 8: ...hown in Figure 3 5 The counter counts repeatedly from BOTTOM to TOP and then to BOTTOM When the counter hits BOTTOM or TOP the counter changes direction immediately holding the BOTTOM and TOP values f...

Страница 9: ...pdate command only has effect on the PERBUF PER registers See section 3 7 for more information about double buffered registers 3 9 2 Force Restart The Force restart command clears the CNT H L register...

Страница 10: ...apshot of the 16 bit CNT H L value at the time CNTL was read Figure 4 1 16 bit read access CNTH CNTL TEMP Rn CNTH CNTL TEMP R n 1 Rn R n 1 1 2 4 2 16 bit Write Figure 4 2 illustrates how to perform a...

Страница 11: ...tes the write operation by writing to CNTH causing the corrupted low byte to be transferred from TEMP to CNTL There are two possible solutions to this problem 1 Make sure that every 16 bit access is p...

Страница 12: ...ded in this way Figure 5 1 Cascading two 16 bit Timer Counter modules TCC1H TCC1L TCC0H TCC0L High word Overflow OVF EVMUX0 Low word OVF Clock signal for high word T C 5 2 Accessing the 32 bit Value W...

Страница 13: ...nterrupt event occurs 2 Start TC by selecting a clock source CLKSEL in CTRLA In this configuration the current timer value can be read directly from the CNT H L register The TC overflow bit indicates...

Страница 14: ...ite the new compare value to CCA H L 8 Wait for the TC Overflow Flag to be set OVFIF in INTFLAGS 9 Clear the TC Overflow flag 10 Go to step 6 Using this sequence the compare value will be updated once...

Страница 15: ...register 11 Read high word input capture value from the TCC1 CCA H L register 12 Combine low word and high word to a 32 bit input capture value 13 Go to step 9 7 Advanced Features In this application...

Страница 16: ...ten in ANSI C and should compile on all compilers with XMEGA support Note that this driver is not written with high performance in mind It is designed as a library to get started with the XMEGA Timer...

Страница 17: ...ARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIR...

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