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14 

AVR1306 

8045A-AVR-02/08 

5. Start the TC by selecting a clock source. 

6. Wait for Input Capture Interrupt Flag A in INTFLAGS to be set. 

7. Read input capture value from the CCA[H:L] register into ‘thisCapture’. 

8. Check bit 15 of ‘thisCapture’. 

9. If bit 15  of ‘thisCapture’ is 1 

a.  Save ‘thisCapture’ in ‘lastRising’ 

10. else 

a.  Calculate total period: 

 

6.4 Using a Timer/Counter for PWM Generation 

Task: Configure TCC0 for pulse width modulation output with varying duty cycle on 
channel A. 

1. Configure PC0 for output by setting bit 0 in PORTC.DIR. 

2. Select the timer period by setting the PER[H:L] register. 

3. Select a waveform generation mode by setting the WGMODE[2:0] bits in  

4. Enable Compare Channel A by setting the CCAEN bit in CTRLB. 

5. Start the TC by selecting a clock source (CLKSEL[3:0] in CTRLA). 

6. Calculate the desired compare value. 

7. Write the new compare value to CCA[H:L]. 

8. Wait for the TC Overflow Flag to be set. (OVFIF in INTFLAGS). 

9. Clear the TC Overflow flag. 

10. Go to step 6. 

 

Using this sequence, the compare value will be updated once every PWM period.  

6.5 Event Counting 

Task: Configure TCC0 to count the number of switch presses on PC0, using event 
channel 0. Generate interrupt after 5 key presses that toggle PC1. 

1. Configure PC0 as input, sense on falling edge. 

2. Configure PC1 as output. 

3. Select PC0 as multiplexer input for event channel 0. 

4. Enable filtering on event channel 0. 

5. Set the period of TCC0 to 4 (to generate overflow interrupt after 5 switch presses). 

6. Enable TCC0 overflow interrupt at low level. 

7. Select event channel 0 as clock source for the TC. 

 

In the TCC0 overflow interrupt service routine, toggle PC1. 

 

In this configuration, the CNT[H:L] register will contain the number of times a switch 
connected to PC0 has been pressed. After 5 presses, an overflow interrupt service 
handler will be triggered, toggling PC1 while CNT[H:L] wraps around to 0. 

Содержание AVR1306

Страница 1: ...ch Timer 1 Double buffered 32 bit operation with 32 bit input capture by timer cascading Event counter Timer overflow and error interrupts and events Input capture interrupts and events 1 Introduction...

Страница 2: ...to I O pin Typical applications include Timing Periodic interrupt event generation Pulse Width Modulation Event time stamping Event counting Signal parameter measurements Period duty cycle etc 3 1 Tim...

Страница 3: ...ed TC_CSEL_DIV1_gc fCLK SYS TC_CSEL_DIV2_gc fCLK SYS 2 TC_CSEL_DIV4_gc fCLK SYS 4 TC_CSEL_DIV8_gc fCLK SYS 8 TC_CSEL_DIV64_gc fCLK SYS 64 TC_CSEL_DIV256_gc fCLK SYS 256 TC_CSEL_DIV1024_gc fCLK SYS 102...

Страница 4: ...ister CCxBUF H L Double buffered registers are covered in detail in section 3 7 When used for input capture the value of the PER register determines how input capture values are interpreted If bit 15...

Страница 5: ...h buffer register has a related buffer valid flag in the CTRLE register The buffer valid flag is set when a new value is written to the corresponding buffer register The flag is cleared when the buffe...

Страница 6: ...the counter value while the counter is running is allowed The write access has higher priority than count clear or reload and will be immediate However if the value written is outside the BOTTOM TOP...

Страница 7: ...s Figure 3 4 shows in this mode of operation the counter counts from BOTTOM to TOP then restarts from BOTTOM The waveform generator output is set on the compare match between the count and compare reg...

Страница 8: ...hown in Figure 3 5 The counter counts repeatedly from BOTTOM to TOP and then to BOTTOM When the counter hits BOTTOM or TOP the counter changes direction immediately holding the BOTTOM and TOP values f...

Страница 9: ...pdate command only has effect on the PERBUF PER registers See section 3 7 for more information about double buffered registers 3 9 2 Force Restart The Force restart command clears the CNT H L register...

Страница 10: ...apshot of the 16 bit CNT H L value at the time CNTL was read Figure 4 1 16 bit read access CNTH CNTL TEMP Rn CNTH CNTL TEMP R n 1 Rn R n 1 1 2 4 2 16 bit Write Figure 4 2 illustrates how to perform a...

Страница 11: ...tes the write operation by writing to CNTH causing the corrupted low byte to be transferred from TEMP to CNTL There are two possible solutions to this problem 1 Make sure that every 16 bit access is p...

Страница 12: ...ded in this way Figure 5 1 Cascading two 16 bit Timer Counter modules TCC1H TCC1L TCC0H TCC0L High word Overflow OVF EVMUX0 Low word OVF Clock signal for high word T C 5 2 Accessing the 32 bit Value W...

Страница 13: ...nterrupt event occurs 2 Start TC by selecting a clock source CLKSEL in CTRLA In this configuration the current timer value can be read directly from the CNT H L register The TC overflow bit indicates...

Страница 14: ...ite the new compare value to CCA H L 8 Wait for the TC Overflow Flag to be set OVFIF in INTFLAGS 9 Clear the TC Overflow flag 10 Go to step 6 Using this sequence the compare value will be updated once...

Страница 15: ...register 11 Read high word input capture value from the TCC1 CCA H L register 12 Combine low word and high word to a 32 bit input capture value 13 Go to step 9 7 Advanced Features In this application...

Страница 16: ...ten in ANSI C and should compile on all compilers with XMEGA support Note that this driver is not written with high performance in mind It is designed as a library to get started with the XMEGA Timer...

Страница 17: ...ARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIR...

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