AVR1306
5
8045A-AVR-02/08
Table 3-2.
Event channel to input capture channel mapping.
Input capture channel
Global event channel
A N
B
(N + 1) % 8
C (If available)
(N + 2) % 8
D (If available)
(N + 3) % 8
Example 1:
EVSEL3 = 1 and EVSEL[2:0] = 0 means that input capture channels A, B, C and D
are triggered by event channels 0, 1, 2 and 3 respectively.
Example 2:
EVSEL3 = 1 and EVSEL[2:0] = 6 means that input capture channels A, B, C and D
are triggered by event channels 6, 7, 0 and 1 respectively.
If the event source is subject to noise, e.g. caused by the bouncing of an external
switch, it is possible to enable digital filtering on the event channel. See application
note AVR1001 for more information on the event system and its digital filtering
capabilities.
3.7 Double Buffered Registers
The PER[H:L] and CCx[H:L] registers in the TC modules are double buffered. They
have dedicated buffer registers named PERBUF[H:L] and CCxBUF[H:L].
Using the PER[H:L] register as an example: when writing to PER[H:L] directly, the
value will be updated immediately. If the value is instead written to PERBUF[H:L], the
value of PER[H:L] will not be updated instantly, but instead transferred from
PERBUF[H:L] on the next UPDATE condition. Each buffer register has a related
“buffer valid” flag in the CTRLE register. The buffer valid flag is set when a new value
is written to the corresponding buffer register. The flag is cleared when the buffer
register is copied to its destination. This ensures that only new values are copied.
It is also possible to lock the automatic update from buffer registers. This enables
simultaneous updates of several registers at one update condition. Setting the Timer
Lock Update (LUPD) bit in the CTRLE register enables update locking.
When the TC module is used for PWM, the buffering is typically used to make sure
that the duty cycles are not altered in the middle of a PWM period, and to synchronize
changes to all PWM channels. New compare/TOP values are typically written to the
buffer registers instead of writing directly to the CCx registers. This way, all PWM
channels can be updated at the same time (on the UPDATE event).
In Input Capture mode, the input capture values are double-buffered. A new input
capture-value is first put in the CCxBUF[H:L] register. Values stored in CCxBUF[H:L]
are transferred to CCx[H:L] if the CCIFx flag is not set. The CCIFx flag is cleared
automatically when CCx[H:L] is read. In practice, this means that the user only needs
to read the CCx[H:L] register, while the rest is handled automatically.
3.8 Modes of Operation
The TC has six different modes of operation:
