65
8210C–AVR–09/11
Atmel AVR XMEGA D
When the DFLL is enabled, it controls the ratio between the reference clock frequency and the
oscillator frequency. If the internal oscillator runs too fast or too slow, the DFLL will decrement or
increment its calibration register value by one to adjust the oscillator frequency. The oscillator is
considered running too fast or too slow when the error is more than a half calibration step size.
Figure 6-7.
Automatic run-time calibration.
The DFLL will stop when entering a sleep mode where the oscillators are stopped. After wake
up, the DFLL will continue with the calibration value found before entering sleep. The reset value
of the DFLL calibration register can be read from the production signature row.
When the DFLL is disabled, the DFLL calibration register can be written from software for man-
ual run-time calibration of the oscillator.
6.8
PLL and External Clock Source Failure Monitor
A built-in failure monitor is available for the PLL and external clock source. If the failure monitor
is enabled for the PLL and/or the external clock source, and this clock source fails (the PLL
looses lock or the external clock source stops) while being used as the system clock, the device
will:
• Switch to run the system clock from the 2MHz internal oscillator
• Reset the oscillator control register and system clock selection register to their default values
• Set the failure detection interrupt flag for the failing clock source (PLL or external clock)
• Issue a non-maskable interrupt (NMI)
If the PLL or external clock source fails when not being used for the system clock, it is automati-
cally disabled, and the system clock will continue to operate normally. No NMI is issued. The
)
(
RCnCREF
RCOSC
f
f
hex
COMP
=
DFLL CNT
COMP
0
t
RCnCREF
Frequency
OK
RCOSC fast,
CALA decremented
RCOSC slow,
CALA incremented
clk
RCnCREF