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ATmega161(L)
1228B–09/01
• Bit 2
–
BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is cleared by a Power-on Reset or by
writing a logical “0” to the flag.
• Bit 1
–
EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is cleared by a Power-on Reset or by
writing a logical “0” to the flag.
• Bit 0
–
PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is cleared only by writing a logical “0”
to the flag.
To make use of the reset flags to identify a reset condition, the user should read and
then clear the MCUSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the reset
flags.
Interrupt Handling
The ATmega161 has two 8-bit Interrupt Mask control registers; GIMSK (General Inter-
rupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled or the
flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is present.
Note that the status register is not automatically stored when entering an interrupt rou-
tine or restored when returning from an interrupt routine. This must be handled by
software.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles, the program vector address for the actual interrupt
handling routine is executed. During this four-clock-cycle period, the Program Counter
(13 bits) is pushed onto the Stack. The vector is normally a jump to the interrupt routine,
and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-
cycle instruction, this instruction is completed before the interrupt is served. If an inter-
rupt occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by four clock cycles.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack
Pointer is incremented by 2, and the I-flag in SREG is set. When AVR exits from an
interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
