Atmel AT90S8414, Руководство пользователя

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AT90S8414
Preliminary
4-41
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the
high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU
receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit
register read operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If
Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the clock cycle
after it is preset with the written value.
TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1AH AND OCR1AL
Bit 15 14 13 12 11 10 9 8
$2B MSB OCR1AH
$2A LSB OCR1AL
7 6 5 4 3 2 1 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1BH AND OCR1BL
Bit 15 14 13 12 11 10 9 8
$29 MSB OCR1BH
$28 LSB OCR1BL
7 6 5 4 3 2 1 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1.
Actions on compare matches are specified in the Timer/Counter1 Control and Status register.
Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used
when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the low byte,
OCR1AL or OCR1BL, the data is temporarily stored in the TEMP register. When the CPU writes the high byte,
OCR1AH or OCR1BH, the TEMP register is simultaneously written to OCR1AL or OCR1BL. Consequently, the low
byte OCR1AL or OCR1BL must be written first for a full 16-bit register write operation.