Atmel AT90S8414, Руководство пользователя

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AT90S8414 Preliminary
Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two
register operands is executed, and the result is stored back to the destination register.
System Clock Ø
T1 T2 T3 T4
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Store Result in Register
Figure 21: Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
System Clock Ø
T1 T2 T3 T4
Internal Address Bus
Internal Data Bus (read)
Internal Write Signal
Internal Read Signal
Internal Data Bus (write)
Figure 22: On-Chip Data SRAM Access Cycles
The external data SRAM access is performed in two System Clock cycles as described in Figure 23.