Atheros AP222A, Руководство пользователя

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COMPANY CONFIDENTIAL 5
Figure 1 Fusion Top Level Block Diagram
1.3 Lower MAC
The Lower MAC portion consists of two main components: The Hardware Abstraction Layer (HAL), and the
Atheros Device Object (ATH). The HAL contains all chip-specific settings and procedures that are performed
to initialize and operate the device. The ATH layer is responsible for managing the data flow into the input
queues of the hardware, as well as managing lower layer protocols, such as Block ACK processing.
1.3.1 HAL
HAL provides low-level primitives to program Atheros chipsets. HAL abstraction will allow runtime support of
multiple chipset families and defines a common body of functions between chipsets with chipset differences
being handled in specific components. Only low-level driver components can interface directly with HAL.
1.3.2 ATH
ATH_DEV module implements the low level MAC functionalities including:
© Unified transmit and receive path for both legacy and 11n chipsets.
© Advanced 11n MAC features: aggregation, RIFS, MIMO power save, etc.
©
802.11 network power save and device power state (D0-D3) management.
© Beacon generation and TSF management.
© Wake-On-Wireless support.
©
Key cache management.
© RfKill, Customized LED and GPIO algorithms
ATH_DEV can be accessed through Atheros device object interface (section 1.2) by protocol shim layer.
1.3.3 Rate Control
The rate control algorithm attempts to transmit unicast packets at the optimum data rate. If there are changes in
the propagation channel, the rate control algorithm will automatically step up or down to a data rate that allows
reliable transmission at the fastest possible rate. The rate control can only be accessed by ath_dev, and should
not by protocol stacks.