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Publication No. 981050 REV. A

PXIe-1209 User Manual

Astronics Test Systems

Identification and Configuration Registers 6-3

Interrupt Control

PXIe-

1209

Reg. 02

Bit

10 9 8 7 6 5 4 3 2 1 0

Write

MIEN

- - - - - - IT - - - - - -

BIEN

RIEN

Read

MIEN

VL4X VL2X DL4X DL2X

EOB RDI

BIEN RIEN

MIEN



Master Interrupt Enable (0 = disabled (default), 1 = enable)

VL4X



Internal VCXO 4X DLL Lock (0 = locked, 1 = not locked)

VL2X



Internal VCXO 2X DLL Lock (0 = locked, 1 = not locked)

DL4X



Internal DDS 4X DLL Lock (0 = locked, 1 = not locked)

DL2X



Internal DDS 2X DLL Lock (0 = locked, 1 = not locked)



Interrupt Type (0 = Type A, software-end-of-interrupt (default), 1 = Type C,

hardware-end-of-interrupt)

EOB



End of Burst (1 = EOB occurred (write a 1 to this bit to clear))

RDI



Ready Interrupt (1 = Ready bit went high (write a 1 to this bit to clear))

BIEN



End of Burst Interrupt Enable (0 = disabled (default), 1 = enabled)

RIEN



Ready Interrupt Enable (0 = disabled (default), 1 = enabled)

Notes:

1. These bits are for diagnostic purposes only. They indicate proper locking of the internal DLL

clocks. DDS locking (DL2X & DL4X) will not occur when FGM = 0 (direct DDS mode).

2. When using Type C interrupts (IT = 1), the interrupt pending bits 7-0 are presented as the

interrupt vector during the interrupt acknowledge cycle. The interrupt is also disabled and
must be re-enabled during the interrupt service routine.

Содержание PXIe-1209

Страница 1: ...28 949 859 8999 Fax 949 859 7139 atsinfo astronics com atssales astronics com atshelpdesk astronics com http www astronicstestsystems com Copyright 2017 by Astronics Test Systems Inc Printed in the Un...

Страница 2: ...tion s of any product or part without Astronics Test Systems express written consent or misuse of any product or part The warranty also does not apply to fuses software non rechargeable batteries dama...

Страница 3: ...y procurement of products from Astronics Test Systems TRADEMARKS AND SERVICE MARKS All trademarks and service marks used in this document are the property of their respective owners Racal Instruments...

Страница 4: ...ion cord or a three prong two prong adapter This will defeat the protective feature of the third conductor in the power cord Maintenance and calibration procedures sometimes call for operation of the...

Страница 5: ...te 1 5 Pulse Width 1 5 Pulse Delay and Double Pulse Spacing 1 5 Single Pulse or Double Pulse 1 5 Run Modes 1 5 Pulse Output 1 6 Sync Out 1 6 External Trigger 1 6 External Gate 1 6 External Reference C...

Страница 6: ...ntinuous and Burst Modes 4 3 Follow Trigger Mode 4 3 Pulse Gating 4 3 Calibration 4 3 Reference Disciplining 4 4 Interrupts 4 4 Chapter 5 5 1 Software Operation 5 1 Using the Soft Front Panel 5 1 Star...

Страница 7: ...cing Low 6 8 Double Pulse Spacing Mid 6 8 Double Pulse Spacing High 6 8 Burst Count Low 6 9 Burst Count High 6 9 Output Amplitude Low Level 6 9 Output Amplitude Low Level 6 9 Slew Rate 6 10 Input Thre...

Страница 8: ...PXIe 1209 User Manual Publication No 981050 REV A iv Astronics Test Systems The page was left intentionally blank...

Страница 9: ...anel 1 8 Figure 5 1 Starting Soft Front Panel 5 1 Figure 5 2 RI1209e Main Panel 5 2 Figure 5 3 Instrument Menu 5 3 Figure 5 4 Configure Menu 5 3 Figure 5 5 Pulse Output Configuration Window 5 4 Figure...

Страница 10: ...PXIe 1209 User Manual Publication No 981050 REV A vi Astronics Test Systems The page was left intentionally blank...

Страница 11: ...Publication No 981050 REV A PXIe 1209 User Manual Astronics Test Systems vii List of Tables Table 6 1 I O Address Map Command Summary 6 1...

Страница 12: ...PXIe 1209 User Manual Publication No 981050 REV A viii Astronics Test Systems DOCUMENT CHANGE HISTORY Revision Date Description of Change Initial Astronics Test Systems release...

Страница 13: ...y Within each channel the internal base clock can be disciplined to an external reference clock for long term stability The PXIe 1209 can be used in a wide variety of applications including functional...

Страница 14: ...r devices and variety of other digital and analog electronics to provide the pulse generation function Register based commands are received through the PXI interface and acted upon either directly by...

Страница 15: ...The internal bus interfaces are not user accessible Pulse and Timing Control Logic The pulse and timing control logic provides the main control and generation of the raw pulse It contains the user pr...

Страница 16: ...erence control from an external source The inputs have switch selectable input impedance and threshold level control Backplane Trigger Signals Four backplane PXI trigger signals are provided via trigg...

Страница 17: ...econd pulse if Double Pulse is enabled is programmable using the pulse delay and double pulse spacing registers Single Pulse or Double Pulse The output pulse can be either a single or a double pulse I...

Страница 18: ...ition can be used Additionally the output pulse can follow the pulse width and period of the trigger input signal External Gate The module can be configured to enable pulsing only during the presence...

Страница 19: ...ignals A B Input Impedance These switches select the input impedance of the signal A and signal B front connector signals Input Signal A Impedance Switch INA 100 K OFF 50 ON Input Signal B Impedance S...

Страница 20: ...de ON Special Mode 2 Switch CONFIG 2 Undefined OFF Undefined ON CONFIG Switch 4 is not used Input Output Signals The front panel input output signals for each channel are as shown in Figure 1 5 and ar...

Страница 21: ...is input is software configurable as the trigger gate or reference clock signal The threshold level and input active high low are programmable The input impedance is switch selectable SYNC This MCX co...

Страница 22: ......

Страница 23: ...ise specified Parameter Conditions Min Limit Typ Max Units Dynamic Performances Pulse Frequency Internal Clock Range 0 093 100M Hz Resolution 0 093 Hz Accuracy 1 without reference disciplining 0 01 Pu...

Страница 24: ...rammable 1 100 or 10M Hz Time to discipline lock after 10 minute module warm up 30 60 sec Notes 1 The frequency accuracy and long term stability can be improved by using an external precision referenc...

Страница 25: ...s of the module are in conformance with PXI Industry Standard per PXI Systems Alliance The nominal dimensions are 160 mm long by 100 mm wide Bus Compliance The module complies with the PXI Express Har...

Страница 26: ...ifications 2 4 Astronics Test Systems CE Certifications Emissions Immunity EN61326 1997 A1 1998 Class A Safety EN61010 1 1993 A2 1995 MTBF MIL HDBK 217 FN2 GB GC 25 379878 hrs Mechanical Weight 1 26 l...

Страница 27: ...s NOT hot swappable The power to the PXIe chassis must be turned off before installing a PXIe 1209 Plugging the module in before the power is off may result in damage to the electronics The PXIe 1209...

Страница 28: ...VISA WinNT ri1209e To install the PXI device driver 1 Use the Windows explorer to navigate to the Windows Driver subdirectory 2 Right mouse click on the file ri1209e inf 3 Select Install Installing th...

Страница 29: ...E folder if you do NOT have a version of the LabWindows CVI run time engine installed on your computer The executable soft front panel requires the LabWindows CVI run time engine to work properly b Se...

Страница 30: ...PXIe 1209 User Manual Publication No 981050 REV A Installation 3 4 Astronics Test Systems This page was left intentionally blank...

Страница 31: ...st be given when programming these values To prevent a pulse parameter from changing until the entire value is written the order of the write operations is important The internal logic is configured t...

Страница 32: ...ingle or Double pulse sequence so this jitter does not occur Frequency Internal Pulse Repetition Rate The internal pulse repetition rate can be derived directly from the DDS output or controlled by a...

Страница 33: ...ter to Follow Trigger Input causes the output pulse to follow both the pulse width and period of the selected Trigger Source specified in the Trigger Gate Control register This feature can be used to...

Страница 34: ...rence clock every three seconds If the module temperature is not stable the disciplining logic may require longer to achieve lock and may transition out of lock Since the purpose of reference discipli...

Страница 35: ...over the PXIe 1209 to allow instrument operation All major functions are provided Starting the Soft Front Panel The Soft Front Panel application is installed when you install the LabWindows CVI drive...

Страница 36: ...side of the main panel In order to generate a pulse you must set the high and low amplitude the pulse width and pulse frequency You must then push the Enable and Run buttons You may also generate a pu...

Страница 37: ...nt Configure and Help menus The Instrument menu is shown below Figure 5 3 Instrument Menu The selections available from this menu are Select choose a different 1209e to control Reset Reset the instrum...

Страница 38: ...often the main panel is refreshed Frequency Generation Mode select how the pulse frequency is generated The Configure sub menu items provide access to the various configurable aspects of the instrumen...

Страница 39: ...be selected as either an input to or output from the pulse generator The choices are Trigger Input this is a trigger input to the module Output pulse the pulse output is routed here Output sync the sy...

Страница 40: ...trigger connect the output is routed to an on board trigger interconnection module and so could be connected to M Trigger B of this pulse generator or M Trigger A or M Trigger B of the alternate pulse...

Страница 41: ...2 A input for PGEN 2 enables the pulse output A low level means that the voltage at the input is below the programmed threshold by the Input A threshold setting of the Front Panel Inputs configuration...

Страница 42: ...th a falling edge on the IN 1 B input for PGEN 1 or IN 2 B input for PGEN 2 triggers the pulse generator Front Panel Signal A rising edge An input signal which crosses the programmed Input A Threshold...

Страница 43: ...ain front panel next to the Update button must be checked The Frequency Generation Mode menu item allows the user to select how the pulse frequency is derived It may be Auto DDS or DDS and Divider In...

Страница 44: ...error ViChar errMsg 256 ri1209e_error_message hdl err errMsg printf ri1209e_init returned error code d n err printf error message s n errMsg return err use other functions of the driver done using the...

Страница 45: ...ialize vi You can select this from within a LabVIEW diagram by right mouse clicking and selecting Instrument I O Instr Drivers Astronics ri1209e ri1209e Initialize vi Once in the diagram the VI must b...

Страница 46: ...or PGEN 1 One requirement for using the driver is to wire the instrument handle out output from one VI to the instrument handle input on the next VI A second requirement for using the driver is to wir...

Страница 47: ...ia the ri1209e Close vi will ultimately result in an execution error The use of the ri1209e Close vi as the last VI in the chain is shown in the diagram below The LabVIEW driver contains several execu...

Страница 48: ...t panel you can select Help Find Examples This will launch the NI Example Finder From there you can look under the instruments folder and select the ri1209e Create Continuous Pulse Pair vi You may fin...

Страница 49: ...dress of 0x101000 the register address increment Channel 2 I O register access requires a base address of 0x102000 the register address increment Table 6 1 I O Address Map Command Summary IO REG Incre...

Страница 50: ...PPS Input 10 10MHz Input 11 1PPS Input DET Reference Clock Detected 0 not detected 1 detected REFSEL Reference Clock Source Select if enabled 00 Front Panel Signal A 01 Front Panel Signal B 10 Backpla...

Страница 51: ...IT Interrupt Type 0 Type A software end of interrupt default 1 Type C hardware end of interrupt EOB End of Burst 1 EOB occurred write a 1 to this bit to clear RDI Ready Interrupt 1 Ready bit went high...

Страница 52: ...tput Sync 11 DDS SYNC_IN or DDS SYNC_OUT 3 TRGSEL Trigger Source Select Rising Edge Falling Edge 0000 Software RUN bit default 1 1000 reserved 0001 Front Panel Signal A 1001 Front Panel Signal A 0010...

Страница 53: ...il the high order register is written Frequency Divider Low PXIe 1209 Reg 0C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write 15 Low Order Bits 0 Read 15 Low Order Bits 0 Frequency Divider High PXIe 12...

Страница 54: ...4 3 2 1 0 Write 31 Middle Order Bits 16 Read 31 Middle Order Bits 16 Pulse Width High PXIe 1209 Reg 14 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Not Used 39 High Order Bits 32 Read 0 39 High Ord...

Страница 55: ...ead 31 Middle Order Bits 16 Pulse Delay High PXIe 1209 Reg 1A Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Not Used 39 High Order Bits 32 Read 0 39 High Order Bits 32 Notes 1 Each bit represents 10...

Страница 56: ...5 4 3 2 1 0 Write 31 Middle Order Bits 16 Read 31 Middle Order Bits 16 Double Pulse Spacing High PXIe 1209 Reg 20 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Not Used 39 High Order Bits 32 Read 0...

Страница 57: ...count is one 2 The registers must be written in the order low then high The new burst count does not take effect until the high order register is written Output Amplitude Low Level PXIe 1209 Reg 26 B...

Страница 58: ...l A Level see note Note Each bit represents 39 mV use 10V 28 1 for programming with zero representing 5 0V default 0 5 0V Calibration Control PXIe 1209 Reg 30 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Страница 59: ...ly 0 Read 15 Low Order Bits 0 Reference Count High PXIe 1209 Reg 7A Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write 31 read only 16 Read 31 High Order Bits 16 Notes 1 The count is a 2 s complement int...

Страница 60: ...PXIe 1209 User Manual Publication No 981050 REV A Identification and Configuration Registers 6 12 Astronics Test Systems This page was left intentionally blank...

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