Astronics PXIe-1209, Руководство пользователя

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Publication No. 981050 REV. A PXIe-1209 User Manual
Astronics Test Systems Identification and Configuration Registers 6-1
Chapter 6
Identification and Configuration Registers
I/O Registers
The PXI Offset address space between 0x10000 and 0x100014 is reserved for
general PXI control of the module. The Address Offset for Channel 1 is 0x101000
whereas address offset for Channel 2 is 0x102000.
There are a variety of registers used to configure and control the PXIe-1209
module. These registers are located in the IOSpace. The address map of the
registers for each channel is shown in Table 6-1. Details of the registers are
provided in the following sections.
Channel 1 I/O register access requires a base address of 0x the register
address increment. Channel 2 I/O register access requires a base address of
0x the register address increment.
Table 6-1, I/O Address Map/Command Summary
IO REG
Increment.
(HEX)
REGISTER DESCRIPTION
IO REG
Increment.
(HEX)
REGISTER DESCRIPTION
00 Control/Status 38 Double Pulse Spacing – Low
04 Interrupt Control 3C Double Pulse Spacing – Mid
08 Trigger/Gate Control 40 Double Pulse Spacing – High (7 bits)
0C Version Info* 44 Burst Count – Low
10 DDS Frequency – Low 48 Burst Count – High
14 DDS Frequency – High 4C Amplitude – Low
18 Frequency Divider – Low 50 Amplitude – High
1C Frequency Divider – High 54 Slew Rate
20 Pulse Width – Low 58 Input Threshold Level
24 Pulse Width – Mid 5C Reserved
28 Pulse Width – High (7 bits) 60 Calibration Control
2C Pulse Delay – Low 64 – EC Calibration Registers – Factory Use
Only
30 Pulse Delay – Mid F0-F4 Reference Count Low/High (read
only)
34 Pulse Delay – High (7 bits)