Artesyn Embedded Technology ATCA-7490, Инструкция по установке и эксплуатации

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Maps and Registers
ATCA-7490 Installation and Use (6806800U11F)
127
Table 5-33 Line Status Register (LSR)
LPC IO Address: Base + 5
Bit Description Default Access
0 Receiver data ready (DR) indicator
DR is set whenever a complete incoming character has been
received and transferred into the RBR or the FIFO. DR is cleared by
reading all of the data in the RBR or the FIFO:
1: New data received
0: No new data 0 LPC: r
1 Overrun error (OE) indicator
When OE is set, it indicates that before the character in the RBR was
read, it was overwritten by the next character transferred into the
register. OE is cleared every time the CPU reads the contents of the
LSR. If the FIFO mode data continues to fill the FIFO beyond the
trigger level, an overrun error occurs only after the FIFO is full and
the next character has been completely received in the shift
register. An overrun error is indicated to the CPU as soon as it
happens. The character in the shift register is overwritten but it is
not transferred to the FIFO:
1: Overrun error occurred
0: No overrun error 0 LPC: r
2 Parity Error (PE) indicator
When PE is set, it indicates that the parity of the received data
character does not match the parity selected in the LCR (bit 4). PE
is cleared every time the CPU reads the contents of the LSR. In the
FIFO mode, this error is associated with the particular character in
the FIFO to which it applies. This error is revealed to the CPU when
its associated character is at the top of the FIFO:
1: Parity error occurred
0: No parity error 0 LPC: r